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参数资料
| 型号： | MPC8240LZU200X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352 |
| 文件页数： | 3/58页 |
| 文件大小： | 596K |
| 代理商： | MPC8240LZU200X |
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MPC8240 Integrated Processor Hardware Specications
11
Electrical and Thermal Characteristics
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC8240. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Table 6 and tested for conformance to the
AC specications for that frequency. The processor core frequency is determined by the bus
(PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by
maximum processor core frequency; see Section 1.9, “Ordering Information.”
1.4.2.1 AC Operating Frequency Data
Table 6 provides the operating frequency information for the MPC8240.
1.4.2.2 Clock AC Specications
Table 7 provides the clock AC timing specications as dened in Section 1.4.2.3, “Input AC Timing
Table 6. Operating Frequency
At recommended operating conditions (see Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Characteristic1
200 MHz
250 MHz
Units
Min
Max
Min
Max
Processor frequency (CPU)
100
200
100
250
MHz
Memory bus frequency
33 – 100
MHz
PCI input frequency
25 – 66
MHz
Note:
1
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the
resulting peripheral logic/ memory bus frequency and CPU (core) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description
in Section 1.6, “PLL Conguration,” for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.
Table 7. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3 V
Num
Characteristics and Conditions 1
Min
Max
Unit
Notes
1a
Frequency of operation (PCI_SYNC_IN)
25
66
MHz
1b
PCI_SYNC_IN cycle time
40
15
ns
2,3
PCI_SYNC_IN rise and fall times
—
2.0
ns
2
4
PCI_SYNC_IN duty cycle measured at 1.4 V
40
60
%
5a
PCI_SYNC_IN pulse width high measured at 1.4V
6
9
ns
3
5b
PCI_SYNC_IN pulse width low measured at 1.4V
6
9
ns
3
7
PCI_SYNC_IN jitter
—
150
ps
8a
PCI_CLK[0:4] skew (pin to pin)
—
500
ps
8b
SDRAM_CLK[0:3] skew (pin to pin)
—
350
ps
8
10
Internal PLL relock time
—
100
s
3,4,6
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