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参数资料
| 型号： | MPC8240LZU200X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352 |
| 文件页数： | 30/58页 |
| 文件大小： | 596K |
| 代理商： | MPC8240LZU200X |
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36
MPC8240 Integrated Processor Hardware Specications
System Design Information
1.7.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, GVdd, LVdd, and GND pins of
the MPC8240.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8240.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8240. The trace length may be used to skew or adjust
the timing window as needed. See Motorola Application Note AN1794/D for more information on this
topic.
1.7.6 Pull-up/Pull-down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: DH[0:31], DL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0:31] and
PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be
driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the
system to minimize possible output switching.
The TEST[0:1] pins require pull-up resistors of 120 Ohms or less connected to OVdd.
It is recommended that TEST2 have weak pull-up resistor (2K – 10K Ohms) connected to GVdd.
It is recommended that the following signals be pulled up to OVdd with weak pull-up resistors (2K – 10K
Ohms): SDA, SCL, SMI, SRESET, TBEN, CHKSTOP_IN, TEST3, and TEST4.
It is recommended that the following PCI control signals be pulled up to LVdd with weak pull-up resistors
(2K – 10K Ohms): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, TRDY, and INTA. The
resistor values may need to be adjusted stronger to reduce induced noise on specic board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[0:3], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors enabled only while device is in the reset state:
GNT4/DA5, DL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], PMAA[0:2], and
QACK/DA0. See Table 17 for more information.
The following pins are reset conguration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], and PLL_CFG[0:4]/DA[10:6]. These pins are sampled during reset
to congure the device.
Reset conguration pins should be tied to GND via 1K Ohm pull-down resistors to insure a logic zero level
is read into the conguration bits during reset if the default logic one level is not desired.
Any other unused active-low input pins should be tied to a logic one level via weak pull-up resistors (2K –
10K Ohms) to the appropriate power supply. Unused active-high input pins should be tied to GND via
weak pull-down resistors (2K – 10K Ohms).
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