参数资料
型号: MPC8240LZU200X
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件页数: 28/58页
文件大小: 596K
代理商: MPC8240LZU200X
34
MPC8240 Integrated Processor Hardware Specications
System Design Information
3
In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended
for hardware modeling support. The AC timing specications given in this document do not apply in PLL
Bypass mode.
4
In clock off mode, no clocking occurs inside the MPC8240 regardless of the PCI_SYNC_IN input.
5
Limited due to maximum memory VCO = 225 MHz.
6
Limited due to minimum CPU VCO = 200 MHz.
7
Limited due to minimum memory VCO = 100 MHz.
8
For clarity, range values are shown rounded down to the nearest whole number (decimal place accuracy
removed).
1.7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8240.
1.7.1 PLL Power Supply Filtering
The AVdd, AVdd2, and LAVdd power signals are provided on the MPC8240 to provide power to the
peripheral logic/memory bus PLL, the 603e processor PLL, and the SDRAM clock delay-locked loop
(DLL), respectively. To ensure stability of the internal clocks, the power supplied to the AVdd, and AVdd2,
and LAVdd input signals should be ltered of any noise in the 500kHz to 10MHz resonant frequency range
of the PLLs. Three separate circuits similar to the one shown in Figure 22 using surface mount capacitors
with minimum effective series inductance (ESL) is recommended for AVdd, and AVdd2, and LAVdd
power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are
recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important.
Figure 22. PLL Power Supply Filter Circuit
1.7.2 Power Supply Voltage Sequencing
The notes in Table 2 contain cautions about sequencing external bus voltages and internal voltages of the
MPC8240. These cautions are necessary for the long-term reliability of the part. If they are violated, the
electrostatic discharge (ESD) protection diodes will be forward biased and excessive current can ow
through these diodes. Figure 2 shows a typical ramping voltage sequence where the DC power sources
(voltage regulators or power supplies) are connected as shown in Figure 23. The voltage regulator delay
shown in Figure 2 can be zero if the various DC voltage levels are all applied to the target board at the
same time. The ramping voltage sequence shows a scenario in which the Vdd/AVdd/AVdd2/LAVdd power
Vdd
AVdd, AVdd2, or LAVdd
10
2.2 F
GND
Low ESL surface-mount capacitors
相关PDF资料
PDF描述
MPC8240LZU250X 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352
MPC8240RZU266X 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
MPC8245LZU300X 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
MPC8245LZU350X 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
MPC8270CVVQLDA 32-BIT, 333 MHz, RISC PROCESSOR, PBGA480
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