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参数资料
| 型号： | MPC8240LZU200X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352 |
| 文件页数： | 8/58页 |
| 文件大小： | 596K |
| 代理商： | MPC8240LZU200X |
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16
MPC8240 Integrated Processor Hardware Specications
Electrical and Thermal Characteristics
Notes:
1
All memory and related interface output signal specications are specied from the VM = 1.4 V of the ris-
ing edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in
question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in
2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
PCI_SYNC_IN). See Figure 6.
2
All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.285*OVdd or
0.615*OVdd of the signal in question for 3.3 V PCI signaling levels. See Figure 7.
3
All output timings assume a purely resistive 50 ohm load (see Figure 9). Output timings are measured at
the pin; time-of-ight delays must be added for trace lengths, vias, and connectors in the system.
4
PCI bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0:3], PAR, TRDY, FRAME,
STOP, DEVSEL, PERR, SERR, AD[0:31], REQ[4:0], GNT[4:0], IDSEL, INTA.
5
PCI hold times can be varied; see Section 1.4.2.4.1, “PCI Signal Output Hold Timing,” for information on
programmable PCI output hold times. The values shown for item 13a are for PCI compliance.
6
These specications are for the default driver strengths indicated in Table 4.
.
Figure 9. AC Test Load for the MPC8240
1.4.2.4.1 PCI Signal Output Hold Timing
In order to meet minimum output hold specications relative to PCI_SYNC_IN for both 33 MHz and 66
MHz PCI systems, the MPC8240 has a programmable output hold delay for PCI signals. The initial value
of the output hold delay is determined by the values on the MCP and CKE reset conguration signals.
Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2
conguration register.
12d
SDRAM_SYNC_IN to output valid (for I2C)
—
5.0
ns
1
13a
Output hold, 66 MHz PCI, with MCP in the default logic 1 state and CKE
pulled down to logic 0 state. See Figure 10.
1.0
—
ns
2,4,5
Output hold, 33 MHz PCI, with MCP and CKE in the default logic 1 state.
See Figure 10.
2.0
—
ns
2,4,5
13b
Output hold (all others)
0
—
ns
1
14a
PCI_SYNC_IN to output high impedance (for PCI)
—
14.0
ns
2,4
14b
SDRAM_SYNC_IN to output high impedance (for all others)
—
4.0
ns
1
Table 9. Output AC Timing Specifications (Continued)
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3 V
Num
Characteristic3,6
Min
Max
Units
Notes
OUTPUT
Z0 = 50
OVdd/2 for PCI
RL = 50
PIN
Output measurements are made at the device pin.
GVdd/2 for Memory
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