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参数资料
| 型号： | MPC8240LZU250X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | TBGA-352 |
| 文件页数： | 11/52页 |
| 文件大小： | 542K |
| 代理商： | MPC8240LZU250X |
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MPC8240 (rev0.5) Hardware Specifications
19
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Notes:
1
All memory and related interface output signal specications are specied from the VM = 1.4 V of the ris-
ing edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in
question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in
2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
PCI_SYNC_IN). See Figure 6.
2
All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.285*OVdd or
0.615*OVdd of the signal in question for 3.3 V PCI signaling levels. See Figure 7.
3
All output timings assume a purely resistive 50 ohm load (See Figure 9). Output timings are measured at
the pin; time-of-ight delays must be added for trace lengths, vias, and connectors in the system.
4
PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0–3], PAR, TRDY,
FRAME, STOP, DEVSEL, PERR, SERR, AD[0–31], REQ[4–0], GNT[4–0], IDSEL, INTA.
5
PCI hold times can be varied, see 1.4.3.3.1 “PCI Signal Output Hold Timing” section for information on
programmable PCI output hold times. The values shown for item 13a are for PCI compliance.
6
These specications are for the default driver strengths indicated in Table 4.
.
Figure 9. AC Test Load for the MPC8240
12c
SDRAM_SYNC_IN to Output Valid (For All Others)
—
7.0
ns
1
12d
SDRAM_SYNC_IN to Output Valid (For I2C)
—
5.0
ns
1
13a
Output Hold, 66 MHz PCI, with MCP and CKE pulled-down to logic 0
states. See Table 11.
1.0
—
ns
2,4,5
Output Hold, 33 MHz PCI, with MCP in the default logic 1 state and
CKE pulled-down to logic 0 state. See Table 11.
2.0
—
ns
2,4,5
13b
Output Hold (All Others)
0
—
ns
1
14a
PCI_SYNC_IN to Output High Impedance (For PCI)
—
14.0
ns
2,4
14b
SDRAM_SYNC_IN to Output High Impedance (For All Others)
—
4.0
ns
1
Table 10. Output AC Timing Specifications (Continued)
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic3,6
Min
Max
Units
Notes
OUTPUT
Z0 = 50
OVdd/2
RL = 50
PIN
Output measurements are made at the device pin.
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