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参数资料
| 型号： | MPC8240LZU250X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | TBGA-352 |
| 文件页数： | 33/52页 |
| 文件大小： | 542K |
| 代理商： | MPC8240LZU250X |
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MPC8240 (rev0.5) Hardware Specifications
39
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
power plane is not loaded as much as the OVdd/GVdd power plane and thus Vdd/AVdd/AVdd2/LAVdd
ramps at a faster rate than OVdd/GVdd.
If the system power supply design does not control the voltage sequencing, the circuit of Figure 23 can be
added to meet these requirements. The MUR420 diodes of Figure 23 control the maximum potential
difference between the 3.3 bus and internal voltages on power-up and the 1N5820 Schottky diodes regulate
the maximum potential difference on power-down.
Figure 23. Example Voltage Sequencing Circuits
1.7.3 Power Supply Sizing
The power consumption numbers provided in Table 5 do not reect power from the OVdd and GVdd power
supplies which are non-negligible for the MPC8240. In typical application measurements, the OVdd power
ranged from 200 to 600 mW and the GVdd power ranged from 300 to 900 mW. The ranges’ low end power
numbers were results of the MPC8240 performing cache resident integer operations at the slowest
frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. The OVdd high end range’s value resulted
from the MPC8240 performing continuous ushes of cache lines with alternating ones and zeroes to PCI
memory. The GVdd high end range’s value resulted from the MPC8240 operating at the fastest frequency
combination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with
alternating ones and zeroes on 64 bit boundaries to local memory.
1.7.4 Decoupling Recommendations
Due to the MPC8240’s dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC8240 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC8240 system, and the MPC8240 itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one decoupling
capacitor at each Vdd, OVdd, GVdd, and LVdd pin of the MPC8240. It is also recommended that these
decoupling capacitors receive their power from separate Vdd, OVdd, GVdd, and GND power planes in the
PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only
ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance,
preferably 0508 or 0603, oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd, OVdd, GVdd, and LVdd planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON).
3.3V
MUR420
1N5820
MUR420
1N5820
2.5V
+3.3V
+2.5V
Source
+5V
Source
5V
3.3V
2.5V
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