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参数资料
| 型号： | MPC8240LZU250X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | TBGA-352 |
| 文件页数： | 6/52页 |
| 文件大小： | 542K |
| 代理商： | MPC8240LZU250X |
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14
MPC8240 (rev0.5) Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.3.1 Clock AC Specications
Notes:
1
These specications are for the default driver strengths indicated in Table 4.
2
Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3
Specication value at maximum frequency of operation.
4
Relock time is guaranteed by design and characterization. Relock time is not tested.
5
Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise
and fall times are not tested.
6
Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL
lock after a stable Vdd and PCI_SYNC_IN are reached during the reset sequence. This specication also
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that
HRST_CPU / HRST_CTRL must be held asserted for a minimum of 255 bus clocks after the PLL-relock
time during the reset sequence.
7
DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). Tclk is the period of
one SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization
feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of
loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. tx0 is a xed delay
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristics and Conditions 1
Min
Max
Unit
Notes
1a
Frequency of Operation (PCI_SYNC_IN)
25
66
MHz
1b
PCI_SYNC_IN Cycle Time
40
15
ns
2,3
PCI_SYNC_IN Rise and Fall Times
—
2.0
ns
2
4
PCI_SYNC_IN Duty Cycle Measured at 1.4 V.
40
60
%
5a
PCI_SYNC_IN Pulse Width High Measured at 1.4V
6
9
ns
3
5b
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
6
9
ns
3
7
PCI_SYNC_IN Jitter
—
<150
ps
8a
PCI_CLK[0–4] Skew (Pin to Pin)
—
500
ps
8b
SDRAM_CLK[0–3] Skew (Pin to Pin)
—
350
ps
8
10
Internal PLL Relock Time
—
100
s
3,4,6
15
DLL Lock Range with DLL_EXTEND = 0 disabled (Default)
0 ≤ (NTclk - tloop - tx0) ≤ 7ns
7
16
DLL Lock Range with DLL_EXTEND = 1 enabled
0 ≤ (NTclk - Tclk/2 - tloop -
tx0) ≤ 7
ns
7
17
Frequency of Operation (OSC_IN)
25
66
MHz
18
OSC_IN Cycle Time
40
15
ns
19
OSC_IN Rise and Fall Times
—
5
ns
5
20
OSC_IN Duty Cycle Measured at 1.4 V.
40
60
%
21
OSC_IN Frequency Stability
—
100
ppm
22
OSC_IN VIH (Loaded)
2.0
V
23
OSC_IN VIL (Loaded)
0.8
V
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