参数资料
型号: MPC8245LZU300X
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件页数: 37/60页
文件大小: 620K
代理商: MPC8245LZU300X
42
MPC8245 Integrated Processor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Figure 25. PLL Power Supply Filter Circuit
1.7.2 Power Supply Voltage Sequencing
The notes in Table 2 contain cautions illustrated in about the sequencing of the external bus voltages and
internal voltages of the MPC8245. These cautions are necessary for the long term reliability of the part. If
they are violated, the electrostatic discharge (ESD) protection diodes will be forward biased and excessive
current can ow through these diodes. Figure 2 shows a typical ramping voltage sequence where the DC
power sources (voltage regulators and/or power supplies) are connected as shown in Figure 26. The voltage
regulator delay shown in Figure 2 can be zero if the various DC voltage levels are all applied to the target
board at the same time. The ramping voltage sequence shows a scenario in which the Vdd/AVdd/AVdd2
power plane is not loaded as much as the OVdd/GVdd power plane and thus Vdd/AVdd/AVdd2 ramps at a
faster rate than OVdd/GVdd.
If the system power supply design does not control the voltage sequencing, the circuit of Figure 26 can be
added to meet these requirements for designs with Vdd/AVdd/AVdd2 = 2.0V ± 100 mV. The MUR420
diodes of Figure 26 control the maximum potential difference between the 3.3V bus and internal voltages
on power-up and the 1N5820 Schottky diodes regulate the maximum potential difference on power-down.
Figure 26. Example Voltage Sequencing Circuits
If the system power supply design does not derive LVdd and OVdd from the same power supply reference
(e.g. LVdd = OVdd = 3.3V but LVdd is externally provided or LVdd = 5.0V and OVdd = 3.3V), the circuits
of Figure 27 can be added to meet the requirements of Caution 10 of Table 2 and Figure 2. The MUR420
diodes of Figure 27 control the maximum potential difference between the LVdd voltage and the 3.3V
OVdd voltage.
Vdd
AVdd or AVdd2
10
2.2 F
GND
Low ESL surface mount capacitors
3.3V
1N5820
MUR420
1N5820
2.0V
+3.3V
+2.0V
Source
+5V
Source
5V
3.3V
2.0 V
MUR420
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