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参数资料
| 型号： | MPC8245LZU300X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件页数： | 39/60页 |
| 文件大小： | 620K |
| 代理商： | MPC8245LZU300X |
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44
MPC8245 Integrated Processor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8245.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8245. The trace length may be used to skew or adjust
the timing window as needed. See Motorola application note AN1794/D for more information on this
topic. Note that there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement. (See Table 9).
1.7.6 Pull-up/Pull-down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: MDH[0–31], MDL[0–31], and
PAR[0–7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0–31],
and PAR[4–7]) will be disabled, and their outputs will drive logic zeros when they would otherwise
normally be driven. For this mode, these pins do not require pull-up resistors, and should be left
unconnected by the system to minimize possible output switching.
The TEST0 pin requires a pull-up resistor of 120 Ohms or less connected to OVdd.
It is recommended that RTC have weak pull-up resistor (2K – 10K Ohms) connected to GVdd.
It is recommended that the following signals be pulled up to OVdd with weak pull-up resistors (2K – 10K
Ohms):
SDA,
SCL,
SMI,
SRESET/SDMA12,
TBEN/SDMA13,
CHKSTOP_IN/SDMA14,
TRIG_IN/RCS2, TRIG_OUT/RCS3, and DRDY
It is recommended that the following PCI control signals be pulled up to LVdd with weak pull-up resistors
(2K – 10K Ohms): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor
values may need to be adjusted stronger to reduce induced noise on specic board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3–0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 16 for more information.
The following pins have internal pull-up resistors enabled only while device is in the reset state:
GNT4/DA5, DL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0–2], PMAA[0–2], and
QACK/DA0. See Table 16 for more information.
The following pins are reset conguration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0–2], PMAA[0–2], SDMA[1–0], and PLL_CFG[0–4]/DA[10–6]. These pins are
sampled during reset to congure the device.
Reset conguration pins should be tied to GND via 1K Ohm pull-down resistors to insure a logic zero level
is read into the conguration bits during reset if the default logic one level is not desired.
Any other unused active low input pins should be tied to a logic one level via weak pull-up resistors (2K –
10K Ohms) to the appropriate power supply listed in Table 16. Unused active high input pins should be
tied to GND via weak pull-down resistors (2K – 10K Ohms).
1.7.7 PCI Reference Voltage - LVdd
The MPC8245 PCI reference voltage (LVdd) pins should be connected to 3.3 ± 0.3 V power supply if
interfacing the MPC8245 into a 3.3 V PCI bus system. Similarly, the LVdd pins should be connected to
5.0 ± 5% V power supply if interfacing the MPC8245 into a 5 V PCI bus system. For either reference
voltage, the MPC8245 always performs 3.3V signaling as described in the PCI Local Bus Specication
(r2.2). The MPC8245 tolerates 5V signals when interfaced into a 5 V PCI bus system.
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