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参数资料
| 型号： | MPC8245TVV266D |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件页数： | 41/60页 |
| 文件大小： | 674K |
| 代理商： | MPC8245TVV266D |
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46
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
System Design Information
The SDMA1 reset conguration pin selects between MPC8245 extended ROM functionality or MPC8240
backwards-compatible functionality on the multiplexed signals: TBEN, CHKSTOP_IN, SRESET,
TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240
backwards-compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended
ROM functionality. Note if using the extended ROM mode, TBEN, CHKSTOP_IN, SRESET, TRIG_IN,
and TRIG_OUT functionality are not available.
The driver names and capability of the pins for the MPC8245 and that of the MPC8240 vary slightly. Refer
to the Drive Capability table (for the ODCR register at 0x73) in the MPC8240 Integrated Processor
Hardware Specications and Table 4 for more details.
The programmable PCI output valid and output hold feature controlled by bits in the power management
conguration register 2 (PMCR2) <0x72> has changed slightly in the MPC8245. For the MPC8240, 3 bits,
PMCR2[6:4] = PCI_HOLD_DEL, are used to select 1 of 8 possible PCI output timing congurations.
PMCR2[6:5] are software controllable but initially are set by the reset conguration state of the MCP and
CKE signals, respectively; PMCR2[4] can be changed by software. The default conguration for
PMCR2[6:4] = 0b110 since the MCP and CKE signals have internal pull-up resistors, but this default
conguration does not select 33 or 66 MHz PCI operation output timing parameters for the MPC8240; this
choice is made by software. For the MPC8245, only 2 bits in the power management conguration register 2
(PMCR2), PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing. PMCR2[5:4] are
software controllable but initially are set by the inverted reset conguration state of the MCP and CKE
signals, respectively. The default conguration for PMCR2[5:4] = 0b00 since the MCP and CKE signals
have internal pull-up resistors and the values from these signals are inverted; this default conguration
selects 66 MHz PCI operation output timing parameters. There are four programmable PCI output timing
congurations on the MPC8245, see Table 11 for details.
Voltage sequencing requirements for the MPC8245 are similar to those for the MPC8240; however, there
are two changes which are applicable for the MPC8245. First, there is an additional requirement for the
MPC8245 that the non-PCI input voltages (Vin) must not be greater than GVDD or OVDD by more than
0.6 V at all times including during power-on reset (see caution 5 in Table 2). Second, for the MPC8245,
LVDD must not exceed OVDD by more than 3.0 V at any time including during power-on reset (see caution
There is no LAVDD input voltage supply signal on the MPC8245 since the SDRAM clock delay-locked loop
(DLL) has power supplied internally. Signal D17 should be treated as a no connect for the MPC8245.
1.7.8
JTAG Conguration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specication, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic.
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相关代理商/技术参数 |
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| MPC8245TVV300D | 功能描述:微处理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245TVV333D | 功能描述:微处理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245TVV350D | 功能描述:微处理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245TZU266D | 功能描述:微处理器 - MPU 266MHz 505.4MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245TZU300D | 功能描述:微处理器 - MPU 300MHz 570MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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