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| 型号： | MPC8308-KIT |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 37/83页 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION FOR MPC830X |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MPU |
| 适用于相关产品： | MPC8308 |
| 所含物品： | 板，线缆，CD，电源 |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
42
Freescale Semiconductor
Enhanced Local Bus
12.1
Enhanced Local Bus DC Electrical Characteristics
This table provides the DC electrical characteristics for the local bus interface.
12.2
Enhanced Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface.
This figure provides the AC test load for the local bus.
Figure 30. Local Bus AC Test Load
Table 36. Local Bus DC Electrical Characteristics at 3.3 V
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2.0
NVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current, (VIN
1 = 0 V or V
IN = LVDD)IIN
—
±5
A
High-level output voltage, (LVDD = min, IOH = –2 mA)
VOH
NVDD – 0.2
—
V
Low-level output voltage, (LVDD = min, IOH = 2 mA)
VOL
—0.2
V
Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned.
Table 37. Local Bus General Timing Parameters
Parameter
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1
—
ns
3, 4
Local bus clock to output valid
tLBKHOV
—3
ns
3
Local bus clock to output high impedance for LD
tLBKHOZ
—4
ns
5
Notes:
1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 NVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Output
Z0 = 50
NVDD/2
RL = 50
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