参数资料
型号: MPC8308VMAFD
厂商: Freescale Semiconductor
文件页数: 5/83页
文件大小: 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
产品培训模块: MPC8308 PowerQUICC II Pro Processor
特色产品: MPC8308 PowerQUICC? II Pro Processor
标准包装: 84
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 473-LFBGA
供应商设备封装: 473-MAPBGA(19x19)
包装: 托盘
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
13
DDR2 SDRAM
MDQ//MDM/MECC output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
—ps
5
266 MHz
900
MDQ//MDM/MECC output hold with respect to
MDQS
tDDKHDX,
tDDKLDX
—ps
5
266 MHz
1100
MDQS preamble start
tDDKHMP
0.75 x tMCK
—ns
6
MDQS epilogue end
tDDKHME
0.4 x tMCK
0.6 x tMCK
ns
6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. For a description and understanding of the timing modifications enabled by use of these bits, see the
MPC8308 PowerQUICC II Pro Processor Reference Manual.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 18. DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
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