参数资料
型号: MPC8314VRAGDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, LEAD FREE, PLASTIC, TEPBGA-620
文件页数: 14/106页
文件大小: 1253K
代理商: MPC8314VRAGDA
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
15
RESET Initialization
6
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8314E.
6.1
RESET DC Electrical Characteristics
Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8314E.
6.2
RESET AC Electrical Characteristics
Table 9 provides the reset initialization AC timing specifications of the MPC8314E.
Table 8. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
2.0
NVDD + 0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ NVDD
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET to activate reset flow
32
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to SYS_CLKIN
when the device is in PCI host mode
32
tSYS_CLKIN
2
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the device is in PCI agent mode
32
tPCI_SYNC_IN
1
HRESET assertion (output)
512
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI host mode
4—
tSYS_CLKIN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of HRESET
0—
ns
Time for the device to turn off POR configuration signals with respect to the
assertion of HRESET
—4
ns
3
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