参数资料
型号: MPC8314VRAGDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, LEAD FREE, PLASTIC, TEPBGA-620
文件页数: 27/106页
文件大小: 1253K
代理商: MPC8314VRAGDA
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
27
Ethernet: Three-Speed Ethernet, MII Management
Figure 12 shows the RMII transmit AC timing diagram.
Figure 12. RMII Transmit AC Timing Diagram
9.2.2.2
RMII Receive AC Timing Specifications
Table 28 provides the RMII receive AC timing specifications.
Figure 13 provides the AC test load.
Figure 13. AC Test Load
Table 28. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 300 mv
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
REF_CLK clock period
tRMX
—20
ns
REF_CLK duty cycle
tRMXH/tRMX
35
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
ns
REF_CLK clock rise VIL(min) to VIH(max)
tRMXR
1.0
4.0
ns
REF_CLK clock fall time VIH(max) to VIL(min)
tRMXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH
symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with
respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or
hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of
a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
REF_CLK
TXD[1:0]
tRMTKHDX
tRMX
tRMXH
tRMXR
tRMXF
TX_EN
Output
Z0 = 50 Ω
NVDD/2
RL = 50 Ω
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