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参数资料
型号： MPC8314VRAGDA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： MICROPROCESSOR, PBGA620
封装： 29 X 29 MM, LEAD FREE, PLASTIC, TEPBGA-620
文件页数： 31/106页
文件大小： 1253K
代理商： MPC8314VRAGDA
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
30
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
9.3.2
MII Management AC Electrical Specifications
Table 31 provides the MII management AC timing specifications.
Input high current
IIH
NVDD = Max
VIN
1 = 2.1 V
—
40
μA
Input low current
IIL
NVDD = Max
VIN = 0.5 V
–600
—
μA
Note:
1. Note that the symbol VIN, in this case, represents the NVIN symbol referenced in Table 1 and Table 2.
Table 31. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 300 mv
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—2.5
—
MHz
2
MDC period
tMDC
—400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
ns
—
MDC to MDIO delay
tMDKHDX
10
—
170
ns
3
MDIO to MDC setup time
tMDDVKH
5—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0—
—
ns
—
MDC rise time
tMDCR
—
10
ns
—
MDC fall time
tMDHF
—
10
ns
—
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the maximum frequency is 4.16 MHz
and the minimum frequency is 0.593 MHz).
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns).
Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V (continued)
Parameter
Symbol
Conditions
Min
Max
Unit
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