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| 型号： | MPC8314VRAGDA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PBGA620 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, TEPBGA-620 |
| 文件页数： | 68/106页 |
| 文件大小： | 1253K |
| 代理商： | MPC8314VRAGDA |
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MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
64
Freescale Semiconductor
PCI Express
16.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 49 is specified using the passive compliance/test measurement load (see
Figure 51) in place of any real PCI Express interconnect + RX component. There are two eye diagrams
that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate
the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always
relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
It is recommended that the recovered TX UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
Crosslink random timeout
Tcrosslink
This random timeout helps
resolve conflicts in crosslink
configuration by eventually
resulting in only one
Downstream and one
Upstream Port.
0—
1
ms
7
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 51 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 49.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50
Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-
Ω probes, see Figure 51). Note that the series capacitors,
CTX, is optional for the return loss measurement.
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 51 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the
PCI Express Base Specifications, Rev 1.0a.
7. See Section 4.2.6.3 of the
PCI Express Base Specifications, Rev 1.0a.
8. MPC8315E SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required
Table 54. Differential Transmitter (TX) Output Specifications (continued)
Parameter
Symbol
Comments
Min
Typical
Max
Units
Notes
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| MPC8315 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8315E PowerQUICC II Pro Processor Hardware Specifications |
| MPC8315CVRADDA | 功能描述:微处理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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