- 您现在的位置：买卖IC网 > PDF目录4073 > MPC8315ECVRAFDA (Freescale Semiconductor)MPU POWERQUICC II PRO 620-PBGA PDF资料下载
参数资料
| 型号： | MPC8315ECVRAFDA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 70/106页 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC II PRO 620-PBGA |
| 标准包装： | 36 |
| 系列： | MPC83xx |
| 处理器类型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 电压： | 1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 620-BBGA 裸露焊盘 |
| 供应商设备封装： | 620-PBGA（29x29） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页当前第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
66
Freescale Semiconductor
PCI Express
Powered down DC input
impedance
ZRX-HIGH-IMP-DC
Required RX D+ as well as D-
DC Impedance when the
Receiver terminations do not
have power.
200 k
—
6
Electrical idle detect
threshold
VRX-IDLE-DET-DIFFp-p
VPEEIDT = 2*|VRX-D+ -VRX-D-|
Measured at the package pins of
the Receiver
65
—
175
mV
—
Unexpected Electrical Idle
Enter Detect Threshold
Integration Time
TRX-IDLE-DET-DIFF-
ENTERTIME
An unexpected Electrical Idle
(Vrx-diffp-p <
Vrx-idle-det-diffp-p) must be
recognized no longer than
Trx-idle-det-diff-entertime to
signal an unexpected idle
condition.
——
10
ms
—
Total Skew
LRX-SKEW
Skew across all lanes on a Link.
This includes variation in the
length of SKP ordered set (e.g.
COM and one to five SKP
Symbols) at the RX as well as
any delay differences arising
from the interconnect itself.
—
20
ns
—
Note:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 52 should be used as the
RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 51). If the clocks to the
RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a
reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect
collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs.
It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not
derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye
diagram.
4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300
mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a
frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference
impedance for return loss measurements for is 50
to ground for both the D+ and D– line (that is, as measured by a vector network
analyzer with 50-
probes, see Figure 52). Note that the series capacitors, C
TX, is optional for the return loss measurement.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is
a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300
mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
Table 55. Differential Receiver (RX) Input Specifications (continued)
Parameter
Symbol
Comments
Min
Typical
Max
Unit
Note
相关PDF资料 |
PDF描述 |
|---|---|
| AM1808BZCE4 | IC ARM9 MPU 361NFBGA |
| AM1808BZWTD4 | IC ARM9 CORTEX MCU 361NFBGA |
| AM1808BZCE3 | IC ARM9 CORTEX MCU 361NFBGA |
| AMC60DRTN-S93 | CONN EDGECARD 120PS DIP .100 SLD |
| AMC60DRTH-S93 | CONN EDGECARD 120PS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8315ECVRAGDA | 功能描述:微处理器 - MPU ENCRYPT RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8315E-RDB | 功能描述:处理器 - 专门应用 PROCESSOR BD RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MPC8315E-RDBA | 功能描述:开发板和工具包 - 其他处理器 PROCESSOR BD RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8315E-RDBA | 制造商:Freescale Semiconductor 功能描述:MPC8315E-RDB Reference Platform |
| MPC8315EVRADDA | 功能描述:微处理器 - MPU ENCRYPT RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。