参数资料
型号: MPC8315ECVRAFDA
厂商: Freescale Semiconductor
文件页数: 8/106页
文件大小: 0K
描述: MPU POWERQUICC II PRO 620-PBGA
标准包装: 36
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 620-BBGA 裸露焊盘
供应商设备封装: 620-PBGA(29x29)
包装: 托盘
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
105
Revision History
28 Revision History
This table summarizes a revision history for this document.
Table 83. Revision History
Revision
Date
Substantive Change(s)
2
11/2011
Corrected Note 11 to pull down.
Note 10 added to RESREF pin. Removed all other instances of Note 10.
Added pull up information.
1
11/2011
Added Notes 4, 5, 6, and 7 in Table 2.
Decoupled PCI_CLK and SYS_CLK_IN rise and fall times.
Relaxed maximum rise/fall time of SYS_CLK_IN from 1.2 ns to 4 ns.
Modified Note 2.
Updated SYS_CLK_IN/PCI_CLK frequency from 66 MHz to 66.67 MHz.
Added Note 4 to Table 9.
Added a note stating “eTSEC should be interfaced with peripheral operating at same voltage level.”
Added a note in Table 26 stating “The frequency of RX_CLK should not exceed the TX_CLK by
more than 300 ppm."
Added a note in Table 29 stating “The frequency of RX_CLK should not exceed the GTX_CLK125
by more than 300 ppm
In Table 42, changed min/max values of tCLK_TOL from 0.05 to 0.005.
Added tLALEHOV parameter to Table 44
Replaced 50 with 50
Added Pull up and Pull down information.
Removed Note 2 from TSEC_MDIO.
Removed configuration 2 from Table 77.
Removed Preliminary from Section 25, “Thermal.
Removed MDIO signal from Section 26.7, “Pull-Up Resistor Requirements” as this signal is not
open drain.
Replaced LCCR with LCRR throughout.
Replaced SYS_CLKIN with SYS_CLK_IN throughout.
Replaced all LBIUCM with LBCM.
Replaced all SYS_CR_CLK_IN and SYS_CR_CLK_OUT with SYS_XTAL_IN and
SYS_XTAL_OUT, respectively. Replaced all USB_CR_CLK_IN and USB_CR_CLK_OUT with
USB_XTAL_IN and USB_XTAL_OUT, respectively.
Added rise/fall time spec for TDM CLK
0
05/2009
Initial public release
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