参数资料
型号: MPC8349EZUAJF
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封装: 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件页数: 107/115页
文件大小: 1228K
代理商: MPC8349EZUAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
91
System Design Information
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
20.7
Pull-Up Resistor Requirements
The MPC8349E requires high resistance pull-up resistors (10 k
is recommended) on open drain type pins
including I2C pins, Ethernet Management MDIO pin and EPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 40. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
20.8
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. The
MPC8349E requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does
not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, generally systems will assert TRST during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to PORESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert TRST without causing
PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these
signals with logic.
The arrangement shown in Figure 40 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is
asserted.
The COP header shown Figure 40 in adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in Figure 40; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
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