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参数资料
型号： MPC8349EZUAJF
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封装： 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件页数： 62/115页
文件大小： 1228K
代理商： MPC8349EZUAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
50
Freescale Semiconductor
I2C
Figure 28 provides the AC test load for the I2C.
Figure 28. I2C AC Test Load
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0 2
—
0.9 3
s
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 Cb
4
300
ns
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb
4
300
ns
Set-up time for STOP condition
tI2PVKH
0.6
—
s
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
s
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1
× OV
DD
—V
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2
× OV
DD
—V
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C
clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that
the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low
(L) state or hold time. Also, tI2PVKH symbolizes I
2C timing (I2) for the time that the data with respect to the stop
condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. MPC8349E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
Table 36. I2C AC Electrical Specifications (continued)
Parameter
Symbol 1
Min
Max
Unit
Output
Z0 = 50
OVDD/2
RL = 50
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