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参数资料
型号： MPC8349EZUAJF
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA672
封装： 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
文件页数： 60/115页
文件大小： 1228K
代理商： MPC8349EZUAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
49
I2C
11 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8349E.
11.1
I2C DC Electrical Characteristics
Table 35 provides the DC electrical characteristics for the I2C interface of the MPC8349E.
11.2
I2C AC Electrical Specifications
Table 36 provides the AC timing parameters for the I2C interface of the MPC8349E. Note that all values
refer to VIH (min) and VIL (max) levels (see Table 35).
Table 35. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OV
DD
OVDD+ 0.3
V
Input low voltage level
VIL
–0.3
0.3
× OV
DD
V
Low level output voltage
VOL
00.2
× OV
DD
V1
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
× C
B
250
ns
2
Pulse width of spikes which must be suppressed
by the input filter
tI2KHKL
050
ns
3
Input current each I/O pin (input voltage is
between 0.1
× OV
DD and 0.9 × OVDD(max)
II
–10
10
A4
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8349E Integrated Host Processor Reference Manual Rev.0 for information on the digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 36. I2C AC Electrical Specifications
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
s
High period of the SCL clock
tI2CH
0.6
—
s
Setup time for a repeated START condition
tI2SVKH
0.6
—
s
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
tI2SXKL
0.6
—
s
Data setup time
tI2DVKH
100
—
ns
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