参数资料
型号: MPC8377VRALG
厂商: Freescale Semiconductor
文件页数: 83/127页
文件大小: 0K
描述: MPU POWERQUICC II PRO 689-PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
59
This table shows the PCI AC timing specifications at 33 MHz.
Input hold from cock
tPCIXKH
0.25
ns
Output clock skew
tPCKOSK
—0.5
ns
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the
PCI 2.3 Local Bus Specifications.
Table 50. PCI AC Timing Specifications at 33 MHz
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1
× OV
DD, VIH = 0.7 × OVDD.
Parameter
Symbol1
Min
Max
Unit
Note
Clock to output valid
tPCKHOV
—11
ns
Output hold from clock
tPCKHOX
2—
ns
Clock to output high impedance
tPCKHOZ
—14
ns
Input setup to clock
tPCIVKH
3.0
ns
Input hold from clock
tPCIXKH
0.25
ns
Output clock skew
tPCKOSK
—0.5
ns
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the
PCI 2.3 Local Bus Specifications.
Table 49. PCI AC Timing Specifications at 66 MHz (continued)
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1
× OVDD, VIH = 0.7 × OVDD.
Parameter
Symbol1
Min
Max
Unit
Note
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