参数资料
型号: MPC8377VRALG
厂商: Freescale Semiconductor
文件页数: 91/127页
文件大小: 0K
描述: MPU POWERQUICC II PRO 689-PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
66
Freescale Semiconductor
Minimum receiver eye
width
The maximum interconnect
media and transmitter jitter that
can be tolerated by the receiver
can be derived as
TRX-MAX-JITTER = 1 –
UPEEWRX = 0.6 UI.
TRX-EYE
0.4
——UI
Maximum time between
the jitter median and
maximum deviation from
the median.
Jitter is defined as the
measurement variation of the
crossing points (VPEDPPRX = 0
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
consecutive unit intervals of
sample data. Jitter is measured
using all edges of the 250
consecutive UI in the center of
the 3500 UI used for calculating
the Tx UI.
TRX-EYE-MEDIAN-to
-MAX-JITTER
0.3
UI
AC peak common mode
input voltage
VPEACPCMRX = |VRXD+
VRXD-|/2 – VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+
– VRX-D-|/2
VRX-CM-ACp
150
mV
Differential return loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at +300 mV and –300
mV, respectively.
RLRX-DIFF
10
dB
Common mode return
loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at 0 V.
RLRX-CM
6—
dB
DC differential input
impedance
RX DC differential mode
impedance.
ZRX-DIFF-DC
80
100
120
Ω
DC Input Impedance
Required RX D+ as well as D-
DC impedance (50 ± 20%
tolerance).
ZRX-DC
40
50
60
Ω
Powered down DC input
impedance
Required RX D+ as well as D–
DC impedance when the
receiver terminations do not
have power.
ZRX-HIGH-IMP-DC
200 k
Ω
Electrical idle detect
threshold
VPEEIDT = 2 × |VRX-D+ -VRX-D-|
Measured at the package pins
of the receiver
VRX-IDLE-DET-DIFF
p-p
65
175
mV
Table 53. Differential Receiver (Rx) Input Specifications (continued)
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
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