参数资料
型号: MPC8540VTAQFC
厂商: Freescale Semiconductor
文件页数: 59/104页
文件大小: 0K
描述: MPU POWERQUICC III 783FCPBGA
标准包装: 36
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1.3V
安装类型: 表面贴装
封装/外壳: 784-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1
58
Freescale Semiconductor
RapidIO
Figure 37. Example Compliance Mask
Y = minimum data valid amplitude
Z = maximum amplitude
1 UI = 1 unit interval = 1/baud rate
X1 = end of zero crossing region
X2 = beginning of data valid window
DV = data valid window = 1 – 2
× X2
The waveform of the signal under test must fall within the unshaded area of the mask to be compliant.
Different masks are used for the driver output and the receiver input allowing each to be separately
specified.
13.3.1 RapidIO Driver AC Timing Specifications
Driver AC timing specifications are provided in Table 47, Table 48, and Table 49. A driver shall comply
with the specifications for each data rate/frequency for which operation of the driver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
The specifications apply for any combination of data patterns on the data signals.
The output of a driver shall be connected to a 100
Ω, ±1%, differential (bridged) resistive load.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7]).
Table 47. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential output high voltage
VOHD
200
540
mV
1
Differential output low voltage
VOLD
–540
–200
mV
1
X2
Z
0
Y
–Y
–Z
1–X2
DV
Differentia
l(V)
Time (UI)
01
X1
1–X1
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