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参数资料
型号： MPC8555VTAPFX
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封装： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件页数： 83/88页
文件大小： 1244K
代理商： MPC8555VTAPFX
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
84
Freescale Semiconductor
Document Revision History
18 Document Revision History
Table 58 provides a revision history for this hardware specification.
19 Device Nomenclature
Ordering information for the parts fully covered by this specification document is provided in
Section 19.1, “Nomenclature of Parts Fully Addressed by this Document.”
19.1
Nomenclature of Parts Fully Addressed by this Document
Table 52 provides the Freescale part numbering nomenclature for the MPC8555E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
Table 51. Document Revision History
Rev. No.
Date
Substantive Change(s)
4
12/2006
Updated Section 2.1.2, “Power Sequencing.”
Updated back page information.
3.2
11/2006
Updated Section 2.1.2, “Power Sequencing.”
Replaced Section 17.8, “JTAG Configuration Signals.”
3.1
10/2005
Table 4: Added footnote 2 about junction temperature.
Table 4: Added max. power values for 1000 MHz core frequency.
Removed Figure 3, “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.”
Table 30: Modified note to tLBKSKEW from 8 to 9
Table 30: Changed tLBKHOZ1 and tLBKHOV2 values.
Table 30: Added note 3 to tLBKHOV1.
Table 30 and Table 31: Modified note 3.
Table 31: Added note 3 to tLBKLOV1.
Table 31: Modified values for tLBKHKT, tLBKLOV1, tLBKLOV2, tLBKLOV3, tLBKLOZ1, and tLBKLOZ2.
Figure 20: Changed Input Signals: LAD[0:31]/LDP[0:3].
Table 43: Modified note for signal CLK_OUT.
Table 43: PCI1_CLK and PCI2_CLK changed from I/O to I.
Table 52: Added column for Encryption Acceleration.
3
8/29/2005
Table 4: Modified max. power values.
Table 43: Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY,
MSRCID4, CLK_OUT, and MDVAL.
2
8/2005
Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as
Table 27 and Table 38 is now listed as Table 31.
Table 7: Added note 2.
Table 14: Modified min and max values for tDDKHMP
16/2005
Table 27: Changed LVdd to OVdd for the supply voltage Ethernet management interface.
Table 4: Modified footnote 4 and changed typical power for the 1000MHz core frequency.
Table 31: Corrected symbols for body rows 9–15, effectively changing them from a high state to a
low state.
0
6/2005
Initial Release.
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