参数资料
型号: MPC8569EVTAUNLB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件页数: 106/126页
文件大小: 2847K
代理商: MPC8569EVTAUNLB
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
High-Speed SerDes Interfaces (HSSI)
Freescale Semiconductor
80
Figure 39. Receiver of SerDes Reference Clocks
The characteristics of the clock signals are as follows:
The supply voltage requirements for XVDD are as specified in Table 3.
The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 39. Each
differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-
Ωtermination to SCOREGND followed by
on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential mode and
single-ended mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC-coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V
÷ 50 = 8 mA)
while the minimum common mode input level is 0.1 V above SCOREGND. For example, a clock with a 50/50
duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50
Ω to SCOREGND DC, or it
exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
2.9.2.3
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs as described below.
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential peak-peak (or
between 200 and 800 mV differential peak). In other words, each signal wire of the differential pair must have a
single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-
or AC-coupled connections.
Input
Amp
50
Ω
50
Ω
SD_REF_CLK
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