- 您现在的位置：买卖IC网 > PDF目录26838 > MPC93H51FA (MOTOROLA INC) PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF资料下载
参数资料
| 型号： | MPC93H51FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件页数： | 11/15页 |
| 文件大小： | 368K |
| 代理商： | MPC93H51FA |
MPC93H51
MOTOROLA
Low Voltage PLL Clock Driver
5
Table 6. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = 0° to 70°C)a
a. AC characteristics apply for parallel output termination of 50
to V
TT
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequencyb
÷ 4 feedback
÷ 8 feedback
Static test mode
b.
The PLL will be unstable with a divide by 2 feedback ratio.
50
25
0
120
60
300
MHz
PLL_EN = 1
PLL_EN = 0
fVCO
VCO Frequency
200
480
MHz
fMAX
Maximum Output Frequencyb
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
240
120
60
MHz
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMRc
c. V
CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range
PCLK, PCLK
1.2
VCC-0.9
V
LVPECL
tr, tfd
d. The MPC93H51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
(
), can only be guaranteed if tr/tf are
within the specified range.
TCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
t()
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
–150
0
+150
+250
ps
PLL locked
tsk(o)
Output-to-Output Skew
300
ps
DC
Output Duty Cycle
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
55
52.5
51.75
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ Output Disable Time
7.0
ns
tPZL, ZH Output Enable Time
6.0
ns
BW
PLL closed loop bandwidth
÷ 2 feedback
÷ 4 feedback
÷ 8 feedback
9.0 – 20.0
3.0 – 9.5
1.2 – 2.1
MHz
-3 db point of
PLL transfer
characteristic
tJIT(CC) Cycle-to-cycle jitter
÷ 4 feedback
Single Output Frequency Configuration
40
ps
RMS value
tJIT(PER) Period Jitter
÷ 4 feedback
Single Output Frequency Configuration
25
ps
RMS value
tJIT() I/O Phase Jitter
30
ps
RMS value
tLOCK Maximum PLL Lock Time
5
ms
相关PDF资料 |
PDF描述 |
|---|---|
| MPC93H51FAR2 | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC93R52ACR2 | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC93R52AC | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC940FA | MPC900 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC940LAC | 940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC93H52AC | 功能描述:时钟发生器及支持产品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。