参数资料
型号: MPC93H51FA
厂商: MOTOROLA INC
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
文件页数: 2/15页
文件大小: 368K
代理商: MPC93H51FA
MPC93H51
10
Low Voltage PLL Clock Driver
MOTOROLA
Figure 11. Propagation delay (tPD, static phase
offset) test reference
Figure 12. Propagation delay (tPD) test reference
Figure 13. Output Duty Cycle (DC)
Figure 14. Output-to-output Skew tSK(O)
Figure 15. Cycle-to-cycle Jitter
Figure 16. Period Jitter
Figure 17. I/O Jitter
Figure 18. Transition Time Test Reference
VCC
VCC÷2
GND
t()
PCLK
Ext_FB
PCLK
VCMR
t()
VCC
VCC÷2
GND
VCC
VCC÷2
GND
TCLK
Ext_FB
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
VCC
VCC÷2
GND
tP
T0
DC = tP/T0 x 100%
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tSK(O)
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
TN
TJIT(CC) = |TN-TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TJIT(P) = |TN-1/f0|
T0
TJIT() = |T0-T1mean|
TCLK
Ext_FB
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
(PCLK)
tF
tR
VCC=3.3V
2.4
0.55
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