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参数资料
| 型号： | MPC93H51FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件页数： | 15/15页 |
| 文件大小： | 368K |
| 代理商： | MPC93H51FA |
MPC93H51
MOTOROLA
Low Voltage PLL Clock Driver
9
two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain
the tight output-to-output skew of the MPC93H51. The
output waveform in Figure 7 “Single versus Dual Line
Termination Waveforms” shows a step in the waveform,
this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the
36
series resistor plus the output impedance does not
match the parallel combination of the line impedances.
The voltage wave launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50W || 50
RS = 36W || 36
R0 = 14
VL = 3.0 ( 25 (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0ns).
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multi-
ple lines the situation in Figure 8 “Optimized Dual Line
Termination” should be used. In this case the series ter-
minating resistors are reduced such that when the paral-
lel combination is added to the output buffer impedance
the line impedance is perfectly matched.
Figure 9. TCLK MPC93H51 AC test reference for V
CC = 3.3V
Figure 10. PCLK MPC93H51 AC test reference
Figure 7. Single versus Dual Waveforms
VOLT
AGE
(V)
OutB
tD = 3.9386
OutA
tD = 3.8956
In
2
4
6
8
10
12
14
TIME (nS)
3.0
2.5
2.0
1.5
1.0
0.5
0
ZO = 50
Figure 8. Optimized Dual Line Termination
10
MPC93H51
OUTPUT
BUFFER
RS = 22
14
+ 22 || 22 = 50 || 50
25
= 25
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC93H51 DUT
VTT
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC93H51 DUT
VTT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC93H52AC | 功能描述:时钟发生器及支持产品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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