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参数资料
| 型号： | MPC9658 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:10的LVCMOS PLL时钟发生器 |
| 文件页数： | 3/12页 |
| 文件大小： | 292K |
| 代理商： | MPC9658 |
MPC9658
TIMING SOLUTIONS
MOTOROLA
Table 1. PIN CONFIGURATION
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
PECL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
VCO_SEL
Input
LVCMOS
Operating frequency range select
BYPASS
Input
LVCMOS
PLL and output divider bypass select
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
Q0-9
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
Negative power supply (GND)
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin VCC_PLL. Please see applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
VCC
Supply
VCC
Table 2. FUNCTION TABLE
Control
Default
0
1
PLL_EN
1
Test mode with PLL bypassed. The reference clock (PCLK)
is substituted for the internal VCO output. MPC9658 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Selects the VCO outputa
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9658 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the output dividers.
VCO_SEL
1
VCO
÷
1 (High frequency range). fREF = fQ0-9 = 2
fVCO
Outputs enabled (active)
VCO
÷
2 (Low frequency range). fREF = fQ0-9 = 4
fVCO
Outputs disabled (high-impedance state) and reset of
the device. During reset the PLL feedback loop is open.
The VCO is tied to its lowest frequency. The length of
the reset pulse should be greater than one reference
clock cycle (PCLK).
MR/OE
0
a.
PLL operation requires BYPASS=1 and PLL_EN=1.
Table 3. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
VIN
VOUT
IIN
IOUT
TS
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Supply Voltage
-0.3
3.9
V
DC Input Voltage
-0.3
VCC+0.3
VCC+0.3
±
20
±
50
V
DC Output Voltage
-0.3
V
DC Input Current
mA
DC Output Current
mA
Storage Temperature
-65
125
°
C
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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