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参数资料
| 型号： | MPC9658 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:10的LVCMOS PLL时钟发生器 |
| 文件页数： | 8/12页 |
| 文件大小： | 292K |
| 代理商： | MPC9658 |
MPC9658
MOTOROLA
TIMING SOLUTIONS
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9658 clock driver is effectively doubled due to its
capability to drive multiple lines.
Figure 6. Single versus Dual Transmission Lines
14
IN
MPC9658
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC9658
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9658 output buffer is more than
sufficient to drive 50
transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9658. The output waveform in Figure 7. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0
÷
(RS+R0 +Z0))
Z0 = 50
|| 50
RS = 36
|| 36
R0 = 14
VL = 3.0 ( 25
÷
(18+14+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Figure 7. Single versus Dual Waveforms
TIME (nS)
V
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 8. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
Figure 8. Optimized Dual Line Termination
14
MPC9658
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22
22
= 50
50
25
= 25
Figure 9. PCLK MPC9658 AC test reference
Differential
Pulse Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9658 DUT
VTT
VTT
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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