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参数资料
| 型号： | MPC9658 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:10的LVCMOS PLL时钟发生器 |
| 文件页数： | 5/12页 |
| 文件大小： | 292K |
| 代理商： | MPC9658 |
MPC9658
TIMING SOLUTIONS
MOTOROLA
Table 6. AC CHARACTERISTICS
(VCC = 3.3V
±
5%, TA = 0
°
C to 70
°
C)a
Symbol
Characteristics
fref
Input reference frequency
PLL mode, external feedback
Min
100
50
Typ
Max
250
125
Unit
MHz
MHz
Condition
PLL locked
PLL locked
÷
2 feedbackb
÷
4 feedbackc
Input reference frequency in PLL bypass moded
VCO lock frequency rangee
Output Frequency
0
250
500
250
125
MHz
MHz
MHz
MHz
fVCO
fMAX
200
100
50
÷
2 feedbackc
÷
4 feedbackd
PLL locked
PLL locked
VPP
VCMRf
tPW,MIN
t(
)
Peak-to-peak input voltage (PCLK)
Common Mode Range (PCLK)
Input Reference Pulse Widthg
Propagation Delay (static phase offset)
500
1.2
2.0
1000
VCC-0.9
mV
V
ns
LVPECL
LVPECL
PCLK to FB_IN
fREF=100 MHz
any frequency
–70
–125
+80
+125
ps
ps
PLL locked
tPD
tsk(O)
DC
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(
)
Propagation Delay (PLL and divider bypass)
Output-to-output Skewh
Output Duty Cyclei
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter fVCO=500 MHz and
÷
2 feedback, RMS (1
σ
)j
fVCO=500 MHz and
÷
4 feedback, RMS (1
σ
)
PLL closed loop bandwidthk
PCLK to Q0-9
1.0
4.0
120
ns
ps
ps
ns
ns
ns
ps
ps
ps
ps
(T
÷
2)–400
0.1
T
÷
2
(T
÷
2)+400
1.0
7.0
6.0
80
80
5.5
6.5
0.55 to 2.4V
BW
÷
2 feedbackc
÷
4 feedbackd
6–20
2–8
MHz
MHz
tLOCK
AC characteristics apply for parallel output termination of 50
to VTT.
÷
2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
÷
4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
In bypass mode, the MPC9658 divides the input reference clock.
The input frequency fref must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO
÷
FB.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(
).
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN
fREF
100% and DCREF,MAX = 100% – DCREF,MIN.
See application section for part-to-part skew calculation in PLL zero-delay mode.
Output duty cycle is DC = (0.5
±
400 ps
fOUT)
100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period.
See application section for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies.
-3 dB point of PLL transfer characteristics.
Maximum PLL Lock Time
10
ms
a
b
c
d
e
f
g
h
i
j
k
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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