参数资料
型号: MPC9658
厂商: Motorola, Inc.
英文描述: 3.3V 1:10 LVCMOS PLL Clock Generator
中文描述: 3.3 1:10的LVCMOS PLL时钟发生器
文件页数: 9/12页
文件大小: 292K
代理商: MPC9658
MPC9658
TIMING SOLUTIONS
MOTOROLA
Figure 10. Output–to–output Skew tSK(O)
Figure 11. Propagation delay (t(PD
)
, static phase
offset) test reference
Figure 12. Output Duty Cycle (DC)
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any simlar delay path within a
single device
The time fromthe PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC
GND
2
VCC
VCC
2
GND
tSK(O)
VCC
VCC
GND
2
tP
T0
DC = tP/T0
x
100%
VCMR =
VCC–1.3V
VCC
VCC
2
GND
t(PD)
PCLK
FB_IN
TJIT(
) =
|
T0–T1mean
|
PCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean in a
randomsample of cycles
Figure 13. I/O Jitter
PCLK
VPP = 0.8V
Figure 14. Cycle–to–cycle Jitter
Figure 15. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
randomsample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a randomsample of cycles
TN
TJIT(CC) =
|
TN–TN+1
|
TN+1
TJIT(PER) =
|
TN–1
/
f0
|
T0
tF
tR
VCC=3.3V
2.4
0.55
Figure 16. Output Transition Time Test Reference
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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