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参数资料
| 型号： | MPC9658 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:10的LVCMOS PLL时钟发生器 |
| 文件页数： | 7/12页 |
| 文件大小： | 292K |
| 代理商： | MPC9658 |
MPC9658
TIMING SOLUTIONS
MOTOROLA
Using the MPC9658 in zero–delay applications
Nested clock trees are typical applications for the
MPC9658. Designs using the MPC9658 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9658 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC9658 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9658 are connected together, the maximum overall
timing uncertainty from the common PCLK input to any output
is:
tSK(PP) = t(
) + tSK(O) + tPD, LINE(FB) + tJIT(
) CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 4. MPC9658 max. device-to-device skew
tPD,LINE(FB)
tJIT(
)
+
t
SK(O)
–t(
)
+t(
)
tJIT(
)
+
t
SK(O)
tSK(PP)
Max. skew
PCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1 ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8. Confidence Facter CF
CF
Probability of clock edge within the distribution
±
1
±
2
±
3
±
4
±
5
±
6
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (
±
3 ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -214 ps to 224 ps relative to PCLK (fREF = 100 MHz,
FB=
÷
4, tjit(
)=8 ps RMS at fVCO = 400 MHz):
tSK(PP) =
[–70ps...80ps] + [–120ps...120ps] +
[(8ps –3)...(8ps 3)] + tPD, LINE(FB)
[–214ps...224ps] + tPD, LINE(FB)
tSK(PP) =
Due to the frequency dependence of the I/O jitter, figure 5.
can be used for a more precise timing performance analysis.
Figure 5. Max. I/O Jitter versus frequency
VCO frequency [MHz]
200
250
300
350
400
450
500
20
15
10
5
0
FB=
÷
2
FB=
÷
4
I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
t
Driving Transmission Lines
The MPC9658 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC
÷
2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9658 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 6. “Single
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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