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参数资料
| 型号： | MPC9772FA |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/17页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| 标准包装： | 160 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:12 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
MPC9772 REVISION 7 JANUARY 8, 2013
7
2013 Integrated Device Technology, Inc.
MPC9772 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
t()
Propagation Delay (static phase offset)(7)
CCLK to FB_IN
6.25 MHz < fREF < 65.0 MHz
65.0 MHz < fREF < 125 MHz
fREF=50 MHz and feedback=8
–3
–4
–166
+3
+4
+166
ps
PLL locked
tSK(O)
Output-to-output Skew(8)
within QA outputs
within QB outputs
within QC outputs
all outputs
100
250
ps
DC
Output Duty Cycle(9)
(T
2) – 200
T
2
(T
2) + 200
ps
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
8
ns
tPZL, LZ
Output Enable Time
8
ns
tJIT(CC)
Cycle-to-cycle Jitter(10)
150
200
ps
tJIT(PER) Period Jitter(11)
150
ps
tJIT()
I/O Phase Jitter RMS (1
)(12)
4 feedback
6 feedback
8 feedback
10 feedback
12 feedback
16 feedback
20 feedback
24 feedback
32 feedback
40 feedback
11
86
13
88
16
19
21
22
27
30
ps
(VCO=400 MHz)
BW
PLL closed loop bandwidth(13)
4 feedback
6 feedback
8 feedback
10 feedback
12 feedback
16 feedback
20 feedback
24 feedback
32 feedback
40 feedback
1.20 – 3.50
0.70 – 2.50
0.50 – 1.80
0.45 – 1.20
0.30 – 1.00
0.25 – 0.70
0.20 – 0.55
0.17 – 0.40
0.12 – 0.30
0.11 – 0.28
MHz
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50
to VTT.
2. In bypass mode, the MPC9772 divides the input reference clock.
3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO (M VCO_SEL).
4. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
fXTAL(min, max) = fVCO(min, max) (M VCO_SEL) and 10 MHz fXTAL 25 MHz.
5. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF, MIN.
6. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only
be guaranteed if tR, tF are within the specified range.
7. Static phase offset depends on the reference frequency. t() [s] = t() [] (fREF 360).
8. Excluding QSYNC output. See application section for part-to-part skew calculation.
9. Output duty cycle is DC = (0.5
200 ps fOUT) 100%. E.g. the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period.
10. Cycle jitter is valid for all outputs in the same divider configuration. See Applications Information section for more details.
11. Period jitter is valid for all outputs in the same divider configuration. See Applications Information section for more details.
12. I/O jitter is valid for a VCO frequency of 400 MHz. See Applications Information section for I/O jitter vs. VCO frequency.
13. –3 dB point of PLL transfer characteristics.
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to +85°C)(1), (2), continued on next page
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
TA = 0°C
to +70°C
TA = –40°C
to +85°C
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