参数资料
型号: MR2A16ATS35CR
厂商: Freescale Semiconductor
文件页数: 14/22页
文件大小: 0K
描述: IC MRAM 4MBIT 35NS 44TSOP
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: MRAM(磁阻 RAM)
存储容量: 4M (256K x 16)
速度: 35ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 44-TSOP(0.400",10.16mm 宽)
供应商设备封装: 44-TSOP II
包装: 带卷 (TR)
Timing Specifications
Table 12. Write Cycle Timing 3 (LB/UB Controlled) 1, 2, 3, 4, 5, 6
Parameter
Symbol
Min
Max
Unit
Write cycle time
7
t AVAV
35
ns
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Byte pulse width (G high)
Byte pulse width (G low)
Data valid to end of write
Data hold time
Write recovery time
t AVBL
t AVBH
t AVBH
t BLEH
t BLWH
t BLEH
t BLWH
t DVBH
t BHDX
t BHAX
0
18
20
15
15
10
0
12
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
14
1
2
3
4
5
6
7
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
MR2A16A Data Sheet, Rev. 6
Freescale Semiconductor
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