参数资料
型号: MSC8122ADSE
厂商: Freescale Semiconductor
文件页数: 18/48页
文件大小: 0K
描述: KIT ADVANCED DEV SYSTEM 8122
标准包装: 1
系列: StarCore
类型: DSP
适用于相关产品: MSC8122
所含物品:
相关产品: MSC8122TVT6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8122TMP6400V-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8122TMP6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8122TMP4800V-ND - DSP 16BIT 300MHZ MULTI 431FCPBGA
MSC8122MP8000-ND - DSP 16BIT 500MHZ MULTI 431FCPBGA
MSC8122VT8000-ND - IC DSP QUAD 16B 500MHZ 431FCPBGA
MSC8122TVT6400V-ND - IC DSP QUAD 16B 400MHZ 431FCPBGA
MSC8122TVT4800V-ND - IC DSP QUAD 16B 300MHZ 431FCPBGA
Electrical Characteristics
In all cases, the power-up sequence must follow the guidelines shown in Figure 8 .
V
3.3 V
B
V DDH (IO)
A
1.2 V
V DD /V CCSYN
t (time)
Figure 8. Power-Up Sequence for V DDH and V DD /V CCSYN
The following rules apply:
1.
2.
2.5.3
During time interval A, V DDH should always be equal to or less than the V DD / V CCSYN voltage level.
The duration of interval A should be kept below 10 ms.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external ( CLKIN and CLKOUT ) clocks. The user must ensure that maximum
frequency values are not exceeded.
Table 7. Maximum Frequencies
Characteristic
Core frequency
Reference frequency (REFCLK)
Internal bus frequency (BLCK)
DSI clock frequency (HCLKIN)
? Core frequency = 300 MHz
? Core frequency = 400/500 MHz
External clock frequency (CLKIN or CLKOUT)
Maximum in MHz
300/400/500
100/133/166
100/133/166
HCLKIN ≤ (min{70 MHz, CLKOUT})
HCLKIN ≤ (min{100 MHz, CLKOUT})
100/133/166
Table 8. Clock Frequencies
Characteristics
Symbol
300 MHz Device
400 MHz Device
500 MHz Device
Min
Max
Min
Max
Min
Max
CLKIN frequency
BCLK frequency
Reference clock (REFCLK) frequency
Output clock (CLKOUT) frequency
SC140 core clock frequency
F CLKIN
F BCLK
F REFCLK
F CLKOUT
F CORE
20
40
40
40
200
100
100
100
100
300
20
40
40
40
200
133.3
133.3
133.3
133.3
400
20
40
40
40
200
166.7
166.7
166.7
166.7
500
Note:
18
The rise and fall time of external clocks should be 3 ns maximum
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
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