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| 型号： | MSC8122ADSE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 39/48页 |
| 文件大小： | 0K |
| 描述： | KIT ADVANCED DEV SYSTEM 8122 |
| 标准包装： | 1 |
| 系列： | StarCore |
| 类型： | DSP |
| 适用于相关产品： | MSC8122 |
| 所含物品： | 板 |
| 相关产品： | MSC8122TVT6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA MSC8122TMP6400V-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA MSC8122TMP6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA MSC8122TMP4800V-ND - DSP 16BIT 300MHZ MULTI 431FCPBGA MSC8122MP8000-ND - DSP 16BIT 500MHZ MULTI 431FCPBGA MSC8122VT8000-ND - IC DSP QUAD 16B 500MHZ 431FCPBGA MSC8122TVT6400V-ND - IC DSP QUAD 16B 400MHZ 431FCPBGA MSC8122TVT4800V-ND - IC DSP QUAD 16B 300MHZ 431FCPBGA |
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TCK
(Input)
V IL
V IH
TDI
708
709
TMS
(Input)
TDO
(Output)
710
Input Data Valid
Output Data Valid
711
TDO
(Output)
Figure 31. Test Access Port Timing Diagram
TCK
(Input)
713
TRST
(Input)
712
Figure 32. TRST Timing Diagram
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8122 device is designed into a system.
3.1
Use the following guidelines for start-up and power-down sequences:
?
?
?
Note:
Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
If possible, bring up V DD / V CCSYN and V DDH together. If it is not possible, raise V DD / V CCSYN first and then bring up
V DDH . V DDH should not exceed V DD / V CCSYN until V DD / V CCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with V DDH going down first and
then V DD / V CCSYN .
This recommended power sequencing for the MSC8122 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply V DDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if V DD rises before V DDH (see Figure 6 ), current can pass from the V DD supply through the
device ESD protection circuits to the V DDH supply. The ESD protection diode can allow this to occur when V DD exceeds V DDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
39
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| MSC8122TMP6400 | 功能描述:数字信号处理器和控制器 - DSP, DSC PBGA PB 1.2V 105C 400MHZ RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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