参数资料
型号: MSC8122ADSE
厂商: Freescale Semiconductor
文件页数: 24/48页
文件大小: 0K
描述: KIT ADVANCED DEV SYSTEM 8122
标准包装: 1
系列: StarCore
类型: DSP
适用于相关产品: MSC8122
所含物品:
相关产品: MSC8122TVT6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8122TMP6400V-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8122TMP6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8122TMP4800V-ND - DSP 16BIT 300MHZ MULTI 431FCPBGA
MSC8122MP8000-ND - DSP 16BIT 500MHZ MULTI 431FCPBGA
MSC8122VT8000-ND - IC DSP QUAD 16B 500MHZ 431FCPBGA
MSC8122TVT6400V-ND - IC DSP QUAD 16B 400MHZ 431FCPBGA
MSC8122TVT4800V-ND - IC DSP QUAD 16B 300MHZ 431FCPBGA
Electrical Characteristics
Table 15. AC Timing for SIU Outputs
Value for Bus Speed in MHz 3
Ref = CLKIN
Ref = CLKOUT
No.
Characteristic
1.1 V
1.2 V
1.2 V
1.2 V
Units
100/
133
133
166
100/133
30 2
31
Minimum delay from the 50% level of the REFCLK for all signals
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK
0.9
6.0
0.8
4.9
0.8
4.9
1.0
5.8
ns
ns
rising edge
32a
Address bus max delay from the 50% level of the REFCLK rising
edge
? Multi-master mode (SIUBCR[EBM] = 1)
? Single-master mode (SIUBCR[EBM] = 0)
6.4
5.3
5.5
4.2
5.5
3.9
6.4
5.1
ns
ns
32b
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50%
6.4
5.1
5.1
6.0
ns
level of the REFCLK rising edge
32c
Address attributes: TT[2–4]/TC max delay from the 50% level of the
6.9
5.7
5.7
6.6
ns
REFCLK rising edge
32d
BADDR max delay from the 50% level of the REFCLK rising edge
5.2
4.2
4.2
5.1
ns
33a
Data bus max delay from the 50% level of the REFCLK rising edge
? Data-pipeline mode
? Non-pipeline mode
4.8
7.1
3.9
6.1
3.7
6.1
4.8
7.0
ns
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
? Data-pipeline mode
? Non-pipeline mode
6.0
7.5
5.3
6.5
5.3
6.5
6.2
7.4
ns
ns
34
Memory controller signals/ALE/CS[0–4] max delay from the 50%
5.1
4.2
3.9
5.1
ns
level of the REFCLK rising edge
35a
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK
6.0
4.7
4.7
5.6
ns
rising edge
35b
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the
5.5
4.5
4.5
5.4
ns
REFCLK rising edge
Notes:
24
1.
2.
3.
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
The maximum bus frequency depends on the mode:
? In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
? In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122.
? To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
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