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参数资料
| 型号： | MT46V16M4 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 4 x 4 banks DDR SDRAM(4 M x 4 x 4组，双数据速率同步动态RAM) |
| 中文描述： | 4梅格× 4 × 4银行DDR SDRAM内存（四米× 4 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 37/69页 |
| 文件大小： | 2369K |
| 代理商： | MT46V16M4 |
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37
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
Figure 25
PRECHARGE Command
PRECHA RGE
The PRECHARGE command (Figure 25) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
t
RP) after
the PRECHARGE command is issued. Input A10 deter-
CS#
WE#
CAS#
RAS#
CKE
A10
BA0,1
HIGH
ALL BANKS
ONE BANK
BA
A0-A9, A11
CK
CK#
BA = Bank Address (if A10 is LOW;
otherwise
“
Don
’
t Care
”
)
t
IS
t
IS
No READ/WRITE
access in progress
Exit power-down mode
Enter power-down mode
CKE
CK
CK#
COMMAND
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
NOP
VALID
T0
T1
T2
Ta0
Ta1
Ta2
VALID
DON
’
T CARE
mines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or
WRITE commands being issued to that bank.
POWER-DOWN (CKE NOT ACTIVE)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times an access is in progress: from the
issuing of a READ or WRITE command until comple-
tion of the burst. Thus a clock suspend is not sup-
ported. For READs, a burst completion is defined when
the Read Postamble is satisfied; For WRITEs, a burst
completion is defined when the Write Postamble is
satisfied.
Power-down (Figure 26) is entered when CKE is
registered LOW. If power-down occurs when all banks
are idle, this mode is referred to as precharge power-
down; if power-down occurs when there is a row active
in any bank, this mode is referred to as active power-
down. Entering power-down deactivates the input
and output buffers, excluding CK, CK#, and CKE. For
maximum power savings, the DLL is frozen. Exiting
power-down requires the device to be at the same
voltage and frequency as when it entered power-down.
However, power-down duration is limited by the
refresh requirements of the device (
t
REFC).
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
Figure 26
Pow er-Dow n
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V4M16 | 1 Meg x 16 x 4 banks DDR SDRAM(1M x 16 x 4组，双数据速率同步动态RAM) |
| MT46V8M8 | 2 Meg x 8 x 4 banks DDR SDRAM(2 M x 8 x 4组，双数据速率同步动态RAM) |
| MT46V2M32LG | DOUBLE DATA RATE DDR SDRAM |
| MT46V2M32V1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4-1 | DOUBLE DATA RATE DDR SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V16M8 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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