- 您现在的位置：买卖IC网 > PDF目录385639 > MT46V4M16 (Micron Technology, Inc.) 1 Meg x 16 x 4 banks DDR SDRAM(1M x 16 x 4组，双数据速率同步动态RAM) PDF资料下载
参数资料
| 型号： | MT46V4M16 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 16 x 4 banks DDR SDRAM(1M x 16 x 4组，双数据速率同步动态RAM) |
| 中文描述： | 1梅格× 16 × 4银行DDR SDRAM内存（100万× 16 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 22/69页 |
| 文件大小： | 2369K |
| 代理商： | MT46V4M16 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
22
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
Data from any READ burst may be truncated with
a BURST TERMINATE command, as shown in Figure
11. The BURST TERMINATE latency is equal to the
READ (CAS) latency, i.e., the BURST TERMINATE
command should be issued
x
cycles after the READ
command, where
x
equals the number of desired data
element pairs (pairs are required by the 2
n
-prefetch
architecture).
Data from any READ burst must be completed or
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TERMI-
NATE command must be used, as shown in Figure 12.
The
t
DQSS (MIN) case is shown; the
t
DQSS (MAX) case
has a longer bus idle time. (
t
DQSS [MIN] and
t
DQSS
[MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank
provided that auto precharge was not activated. The
PRECHARGE command should be issued
x
cycles after
the READ command, where
x
equals the number of
desired data element pairs (pairs are required by the 2
n
-
prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
t
RP
is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
READs (continued)
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V8M8 | 2 Meg x 8 x 4 banks DDR SDRAM(2 M x 8 x 4组，双数据速率同步动态RAM) |
| MT46V2M32LG | DOUBLE DATA RATE DDR SDRAM |
| MT46V2M32V1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4-1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75 | DOUBLE DATA RATE DDR SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V4M32 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32LG | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
发布紧急采购，3分钟左右您将得到回复。