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参数资料
| 型号： | MT49H16M16 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | 热敏电阻 |
| 英文描述： | THERMISTOR PTC 100OHM 110DEG RAD |
| 中文描述： | 低延迟DRAM延迟DRAM |
| 文件页数： | 1/43页 |
| 文件大小： | 652K |
| 代理商： | MT49H16M16 |
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ADVANCE
1
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
2002, Micron Technology, Inc.
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
REDUCED LATENCY
DRAM (RLDRAM)
FEATURES
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q I/O
Cyclic bank addressing for maximum data out
bandwidth
Non-multiplexed addresses
Non-interruptible sequential burst of two (2-bit
prefetch) and four (4-bit prefetch) DDR
Target 600 Mb/s/p data rate
Programmable Read Latency (RL) of 5-8
Data valid signal (DVLD) activated as read data is
available
Data Mask signals (DM0/DM1) to mask first and
second part of write data burst
IEEE 1149.1 compliant JTAG boundary scan
Pseudo-HSTL 1.8V I/O Supply
Internal Auto Precharge
Refresh requirements: 32ms at 100°C junction
temperature (8K refresh for each bank, 64K refresh
command must be issued in total each 32ms)
OPTIONS
Clock Cycle Timing
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
Configuration
8 Meg x 32
(1 Meg x 32 x 8 banks)
16 Meg x 16
(2 Meg x 16 x 8 banks)
Package
144-ball, 11mm x 18.5mm T-FBGA
MARKING
-3.3
-4
-5
MT49H8M32FM
MT49H16M16FM
FM
144-Ball T-FBGA
MT49H8M32 – 1 Meg x 32 x 8 banks
MT49H16M16 – 2 Meg x 16 x 8 banks
For the latest data sheet, please refer to the Micron
Web site:
www.micron.com/dramds
GENERAL DESCRIPTION
The Micron
256Mb Reduced Latency DRAM
(RLDRAM) contains 8 banks x32Mb of memory acces-
sible with 32-bit or 16-bit I/Os in a double data rate (DDR)
format where the data is provided and synchronized with
a differential echo clock signal. RLDRAM does not require
VALID PART NUMBERS
PART NUMBER
MT49H8M32FM-xx
MT49H16M16FM-xx
DESCRIPTION
8 Meg x 32
16 Meg x 16
row/column address multiplexing and is optimized for
fast random access and high-speed bandwidth.
RLDRAM is designed for communication data
storages like transmit or receive buffers in telecommuni-
cation systems as well as data or instruction cache
applications requiring large amounts of memory.
POWER-UP INITIALIZATION
Since the RLDRAM does not have a designated reset
function, the following procedure must be executed in
order to initalize the internal state machine, regulators,
and force the DRAM to be in ready state.
Apply power, then start clock
After power on, an initial pause of 200μs is required
MRS command for 2 clocks and set standard mode
register for 1 clock (2 dummies plus 1 valid MRS set)
8 refresh cycles (minimum), one on each bank and
separated by 2,048 cycles (
t
MRSC must be satisfied
between MRS and first REF command)
Ready for normal operation (
t
RC cycles after the last
refresh command)
相关PDF资料 |
PDF描述 |
|---|---|
| MT49H16M16FM | REDUCED LATENCY DRAM RLDRAM |
| MT49H8M32 | THERMISTOR PTC 100OHM 120DEG RAD |
| MT49H8M32FM | REDUCED LATENCY DRAM RLDRAM |
| MT4C1M16E5DJ-6 | EDO DRAM |
| MT4LC1M16E5DJ-6S | EDO DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT49H16M16BM-4 | 制造商:Micron Technology Inc 功能描述:512MB 64MX72 DDR SDRAM MODULE PBF DIMM 2.5V REGISTERED - Trays |
| MT49H16M16FM | 制造商:MICRON 制造商全称:Micron Technology 功能描述:REDUCED LATENCY DRAM RLDRAM |
| MT49H16M16FM-33 ES | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 256MBIT 1.8V 144PIN UBGA - Trays |
| MT49H16M16FM-33 TR | 制造商:Micron Technology Inc 功能描述:16MX16 RLDRAM PLASTIC FBGA 1.8V COMMON I/O 8 BANKS 1.8V I/O - Tape and Reel |
| MT49H16M16FM-4 | 制造商:Micron Technology Inc 功能描述: 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 256MBIT 1.8V 144FBGA - Trays |
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