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参数资料
| 型号： | MT49H16M16 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | 热敏电阻 |
| 英文描述： | THERMISTOR PTC 100OHM 110DEG RAD |
| 中文描述： | 低延迟DRAM延迟DRAM |
| 文件页数： | 12/43页 |
| 文件大小： | 652K |
| 代理商： | MT49H16M16 |
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12
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
TEST DATA-OUT (TDO)
The TDO output pin is used to serially clock data-out
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure 1.)
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
(See Figure 2.)
PERFORMING A TAP RESET
A RESET is performed by forcing TMS HIGH (V
DD
) for
five rising edges of TCK. This RESET does not affect the
operation of the RLDRAM and may be performed while the
RLDRAM is operating.
At power-up, the TAP is reset internally to ensure that
TDO comes up in a High-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO
pins and allow data to be scanned into and out of the
RLDRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data is
output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure
2. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Bypass Register
0
Instruction Register
0
1
2
3
4
5
6
7
Identification Register
0
1
2
29
30
31
.
.
.
Boundary Scan Register
0
1
2
.
.
x
.
.
.
Selection
Circuitry
Selection
Circuitry
TCK
TMS
TAP Controller
TDI
TDO
x = 103 for all configurations.
Figure 2
TAP Controller Block Diagram
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary “01”
pattern to allow for fault isolation of the board-level serial
test data path.
BYPASS REGISTER
To save time when serially shifting data through regis-
ters, it is sometimes advantageous to skip certain chips.
The bypass register is a single-bit register that can be
placed between the TDI and TDO pins. This allows data to
be shifted through the RLDRAM with minimal delay. The
bypass register is set LOW (V
SS
) when the BYPASS
instruction is executed.
BOUNDARY SCAN REGISTER
The boundary scan register is connected to all the
input and bidirectional pins on the RLDRAM. Several no
connect (NC) pins are also included in the scan register to
reserve pins. The RLDRAM has a 104-bit register.
The boundary scan register is loaded with the contents
of the RAM I/O ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the con-
tents of the I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to one
of the pins on the RLDRAM package. The MSB of the
register is connected to TDI, and the LSB is connected to
TDO.
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