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| 型号： | NCL30105GEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/22页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 80V 350 FOR LED DRV |
| 设计资源： | NCL30105GEVB Gerber Files NCL30105GEVB BOM NCL30105GEVB Schematic |
| 标准包装： | 1 |
| 电流 - 输出 / 通道： | 350mA |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 60V |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCL30105 |
| 其它名称： | NCL30105GEVBOS |
NCL30105
Application Information
Introduction
NCL30105 implements a current ? mode architecture
operated with a constant off time. The internal current set
point and the external sense resistor determine the on time
duration. The off time duration is adjusted with a resistor
connected from the toff pin to ground. The constant off time
operation enables deep continuous conduction mode
operation without requiring slope compensation. The DIM
pin enables the use of a PWM signal to modulate the
switching pattern and adjust the average luminosity. The
SSTART pin creates a soft ? start that reduces the stress on the
power components during startup and enables the use of an
analog dimming signal to set the peak current by adjusting
the SSTART pin voltage.
? Constant Off Time Peak Current ? Mode Operation:
The constant off time technique enables the controller
to operate a converter in deep continuous conduction
mode without requiring slope compensation. The
constant off time technique is inherently immune to
sub ? harmonic oscillations.
? Off Time Adjustment: A pull ? down resistor
connected to the toff pin sets the off time duration.
? Maximum On Time Protection: an internal circuit
monitors the drive signal on time duration. If the drive
on time duration reaches t on(MAX) , the fault up/down
counter is incremented by 1. If the drive on time
duration reaches t on(MAX) during the next clock cycle,
the counter is incremented again. If the drive on time
duration does not reach t on(MAX) due to the current
comparator being triggered during the next drive on
time, the counter is decremented by 1. This sequence
continues until the counter reaches 8. If the counter
reaches 8, the NCL30105 is immediately latched off.
When V CC is forced below V CC(off) and then above
V CC(on) , the latch is reset.
? LED Short ? Circuit Protection: If the CS pin voltage
increases above V ILIM(fault) , the overcurrent comparator
is triggered, which turns off the drive and increments
the fault up/down counter by 1. If the overcurrent
comparator is triggered again during the next drive on
time, the counter is incremented again. If the
overcurrent comparator is not triggered due to the
current comparator being triggered during the next
drive on time, the counter is decremented by 1. This
sequence continues until the counter reaches 8. If the
counter reaches 8, the part is immediately latched off.
When V CC is forced below V CC(off) and then above
V CC(on) , the latch is reset.
? Power On Delay: When V CC reaches V CC(on) , the
t start(delay) timer begins counting, during which the
drive is disabled. When t start(delay) elapses, the SSTART
pin current source is enabled and the soft ? start
sequence begins.
? Soft ? Start Operation: A capacitor connected to the
SSTART pin is charged by an internal current source
after the t start(delay) timer period has elapsed. The
soft ? start period is completed when the SSTART pin
voltage reaches V ILIM *I ratio . The soft ? start capacitor is
discharged during the t start(delay) to ensure the SSTART
pin voltage begins charging from zero.
? Peak Adjustment: Analog dimming is achieved by
forcing the SSTART pin below V ILIM *I ratio , which
lowers the peak current set point. Note: even if the
SSTART pin is forced to 0 V, there is still a minimum
on time every switching cycle. Under this condition, the
minimum on time is the current sense leading edge
blanking time plus the propagation delay to turn off the
MOSFET and the off time is determined by the toff
resistor value.
? Leading Edge Blanking: an internal circuit blinds the
current sense comparator for a few hundred
nanoseconds when the output drive goes high. The LEB
ensures that controller remains insensitive to the
turn ? on voltage spikes observed on the CS pin due to
the free ? wheel diode recovery time.
? Dimming Input: a dedicated pin is provided to PWM
modulate the LED current to reduce the LED
luminosity. The circuit is driven on and off via a 3.3 ? V
logic level signal. The DIM pin can also be used as an
enable/disable pin, since the switching is disabled when
there is a logic low signal applied to this pin.
? Thermal Shutdown: if the junction temperature of the
controller exceeds an internal threshold, the drive is
disabled. The drive remains disabled until the junction
temperature decreases below the internal hysteresis
threshold. The disabling of the drive protects the
controller from destruction due to overheating.
Startup Sequence
When V CC reaches V CC(on) , the NCL30105 maintains the
drive low and the soft ? start capacitor (C SSTART , connected
to the SSTART pin) remains pulled to ground by the internal
pull ? down switch until the startup delay (t start(delay) )
elapses. Once the t start(delay) period has elapsed, the drive is
enabled and a soft ? start sequence begins. The internal
current source begins charging C SSTART and the voltage on
the SSTART pin (V SSTART ) begins increasing. The peak
current set point is equal to V SSTART divided by I ratio . When
V SSTART reaches the voltage that sets the maximum peak
current (V SSTART = V ILIM *I ratio ), the soft ? start sequence is
complete and the peak current set point is equal to V SSTART
divided by I ratio . Figure 22 describes a typical start ? up
sequence.
http://onsemi.com
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