参数资料
型号: NCL30105GEVB
厂商: ON Semiconductor
文件页数: 15/22页
文件大小: 0K
描述: BOARD EVAL 80V 350 FOR LED DRV
设计资源: NCL30105GEVB Gerber Files
NCL30105GEVB BOM
NCL30105GEVB Schematic
标准包装: 1
电流 - 输出 / 通道: 350mA
输出及类型: 1,非隔离
输出电压: 60V
已供物品:
已用 IC / 零件: NCL30105
其它名称: NCL30105GEVBOS
NCL30105
detection during surge tests, the controller uses the same
counter as the maximum on time limitation. Due to the two
different LEB circuits (t LEB and t LEB(fault) ) configuration, if
there is a severe overload, the overcurrent comparator is
triggered first and the counter is incremented. If the
overcurrent comparator is not triggered during the next
clock cycle, the counter is decremented by the current
comparator. Figure 27 depicts the logical arrangement
inside the controller. In the presence of a fast rising signal,
the overcurrent comparator is triggered first since t LEB(fault)
< t LEB . When the overcurrent comparator output goes high,
it resets the PWM latch and increments the counter. The
counter can no longer increment or decrement until the next
switching cycle. If during the time the overcurrent
comparator output is high, t LEB elapses and causes the
current comparator output to go high, the output of the
current comparator is ignored due to the AND gate
connection. Figure 30 illustrates the operation of the CS
logic during an overcurrent fault. Only one up count or one
down count is made per switching cycle.
CS
V ILIM
?
+
Current
Comparator
latch
off
t LEB
t LEB(fault)
+
Overcurrent
Comparator
down
N fault
V ILIM(fault)
?
Q
t on >
t on(MAX)
up
Count to N fault
PWM reset
Figure 27. CS Internal Logic
V CS (t)
t ILIM
Required peak current
V ILIM
V CS (t)
Noise “blanked”
t ILIM
V ILIM
t
t
V ILIM
Comparator
Output
DRV
down
Inadvertant trigger
t LEB
DRV turned off
before required
peak current is
reached
t
V ILIM
Comparator
Output
DRV
t LEB
down
t
t
Figure 28. Circuit without Leading Edge Blanking
t
Figure 29. Circuit with Leading Edge Blanking
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