参数资料
型号: NCL30105GEVB
厂商: ON Semiconductor
文件页数: 19/22页
文件大小: 0K
描述: BOARD EVAL 80V 350 FOR LED DRV
设计资源: NCL30105GEVB Gerber Files
NCL30105GEVB BOM
NCL30105GEVB Schematic
标准包装: 1
电流 - 输出 / 通道: 350mA
输出及类型: 1,非隔离
输出电压: 60V
已供物品:
已用 IC / 零件: NCL30105
其它名称: NCL30105GEVBOS
NCL30105
Thermal Considerations:
The designer must ensure that the junction temperature of
the NCL30105 remains less than the value of the maximum
operating junction temperature in the Maximum Ratings
Table for the worst ? case operating conditions. The
maximum junction temperature is calculated using the
estimated current consumption. The estimated current
consumption is calculated using the following assumptions:
1. The switching frequency is at the maximum of
500 kHz (f SW(MAX) ).
2. The Vcc is at the maximum of 22 V (V CC(MAX) )
3. The gate of the MOSFET is modeled using a 1 nF
capacitor (C g )
4. The non ? switching bias current is at the maximum
of 1.56 mA (I CC2 )
Using these assumptions, the current consumption is
calculated:
I CC(TJMAX) + C g @ V CC @ f SW(MAX) ) I CC2
I CC(TJMAX) + (1 n @ 22 @ 500 k) ) 1.56 m + 12.56 mA
The power dissipation of the NCL30105 is calculated:
P (TJMAX) + I CC(TJMAX) @ V CC(MAX)
P (TJMAX) + 12.56 m @ 22 + 276 mW
The junction temperature is calculated using the
maximum thermal resistance (R q JA(MAX) ) with the
minimum PCB copper area from the maximum ratings table:
T J(rise) + P (TJMAX) @ R q JA(MAX)
T J(rise) + 0.276 @ 178 + 40 o C
Assuming a maximum ambient temperature of 70 ° C
(T ambient ), the maximum junction temperature is calculated:
T J(MAX) + T J(rise) ) T ambient
T J(MAX) + 49 ) 70 + 119 o C
Since this is less than the T SHDN parameter with sufficient
margin, the design is acceptable.
Layout Tips:
Careful layout is critical for all switch ? mode power
supply design. Successful layout includes special
consideration for noise sensitive pins of the controller IC.
For the NCL30105 the following pins should be carefully
routed:
1. Vcc: This pin requires a ceramic decoupling
capacitor (typically 100 nF) and a electrolytic
capacitor (typically 10 m F) to ensure that IC supply
is constant and decoupled from high frequency
noise generated by switching currents.
2. toff: This pin requires a resistor connected to
ground to set the off time. It is not recommended
to leave this pin open or shorted to ground to set
the off time. The connection from the toff pin to
the resistor and from the resistor to ground must be
made as short as possible and connected directly to
the NCL30105 GND pin. High noise nodes and
traces must be routed as far away from this pin as
possible.
3. SSTART: A capacitor is connected to this pin to
set the Soft ? Start time. The connection from the
SSTART pin to the capacitor and from the
capacitor to ground must be made as short as
possible.
4. DIM: A decoupling capacitor may need to be
connected to this pin if it coupled to high noise
traces. The connection from the DIM pin to the
capacitor and from the capacitor to ground must be
made as short as possible. The addition of the
capacitor may affect the response of time of the
DIM signal to the DRV output.
5. CS: If LEB period is not long enough to ensure
predictable operation, a small RC filter may need
to be connected to this pin. The addition of the RC
filter affects the current set point accuracy.
6. DRV: The trace that connects the DRV pin to the
MOSFET must be made as short as possible to
reduce the parasitic inductance of the trace. The
DRV pin switches high currents and the parasitic
inductance can cause higher than expected
voltages to be applied to the gate of the MOSFET.
A small resistor is recommended to be connected
in series with the DRV pin to the gate. The resistor
reduces the effect of the parasitic inductance. The
addition of the resistor may affect the switching
losses of the MOSFET.
http://onsemi.com
19
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