参数资料
型号: NCN6001DTBR2G
厂商: ON Semiconductor
文件页数: 20/36页
文件大小: 0K
描述: IC INTERFACE SMART CARD 20TSSOP
标准包装: 1
应用: 智能卡
接口: 微控制器
电源电压: 2.75 V ~ 5.5 V
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 标准包装
安装类型: 表面贴装
其它名称: NCN6001DTBR2GOSDKR
NCN6001
http://onsemi.com
27
The input clock can be divided by 1/1,
or , depending
upon the specific application, prior to be applied to the smart
card driver. On the other hand, the positive and negative
going slopes of the output clock (CRD_CLK) can be
programmed to optimize the operation of the chip
(Table 10). The slope of the output clock can be
programmed on the fly, independently of either the
CRD_VCC voltage or the operating frequency, but care
must be observed as the CRD_RST will reflect the logic
state present at MOSI/b4 register.
Table 10. OUTPUT CLOCK RISE AND FALL TIME SELECTION
B0
B1
CRD_CLK
Division Ratio
CRD_CLK
SLO_SLP
CRD_CLK
FST_SLP
0
Output Clock = Low
0
1
10 ns (typ.)
2 ns (typ.)
1
0
1/2
10 ns (typ.)
2 ns (typ.)
1
1/4
10 ns (typ.)
2 ns (typ.)
Figure 27. Force CRD_CLK to Low
Figure 28. Force CRD_CLK to Active Mode
Figure 29. CRD_CLK Programming
Note: Waveforms recorded without external compensation
network.
Figure 30. CRD_CLK Operating Low Speed (Top Trace),
Full Speed (Bottom Trace)
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