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| 型号： | NCN6001DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 标准包装： | 1 |
| 应用： | 智能卡 |
| 接口： | 微控制器 |
| 电源电压： | 2.75 V ~ 5.5 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6001DTBR2GOSDKR |
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NCN6001
http://onsemi.com
17
DATA I/O LEVEL SHIFTER
The level shifter accommodates the voltage difference
that might exist between the microcontroller and the smart
card. A pulsed accelerator builtin circuit provides the fast
positive going transient according to the ISO78163
specifications. The basic I/O level shifter is depicted in
Figure 8.
LOGIC AND
LEVEL SHIFT
Q4
Q3
Q2
R2
18 k
Q5
GND
CRD_VCC
13
CRD_IO
20
CRD_VCC
CARD ENABLE
POR
SEQ 1
200 ns
Q1
R1
18 k
EN_RPU
6
I/O
1
VCC
9
VCC
PMOS
U1
VCC
Q5
GND
SYNC
MOSI/b3
MOSI/b2
From MOSI
decoding
Figure 8. Basic I/O Internal Circuit
The transaction is valid when the Chip Select pin is Low,
the I/O signal being Open Drain or Totem Pole on either
sides.
Since the device can operate either in a single or a multiple
card system, provisions have been made to avoid CRD_IO
current overload. Depending upon the selected mode of
operation (ASYNC. or Sync), the card I/O line is
respectively connected to either I/O pin 1, or to the MOSI
register byte bit 2. On the other hand, the logic level present
at the card I/O is feedback to the
mC via the MISO register
bit 3. The logic level present at pin 6 controls the connection
of the internal pullup as depicted in Table 6.
Table 6. I/O PULLUP RESISTOR TRUE TABLE
EN_RPU
I/O Pullup Resistor
Device
Operation
Low
Open, 18 kW disconnected
Parallel Mode
High
Internal 18 kW pullup active
Single Device
NOTE: 18 kW typical value
Figure 9. Typical I/O Rise and Fall Time
NOTE: Both sides of the interface run with open drain load
(worst case condition).
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