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参数资料
| 型号： | NCN6001DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 36/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 标准包装： | 1 |
| 应用： | 智能卡 |
| 接口： | 微控制器 |
| 电源电压： | 2.75 V ~ 5.5 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6001DTBR2GOSDKR |
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NCN6001
http://onsemi.com
9
POWER SUPPLY @ 2.7 V < VCC < 5.5 V (25C to +85C ambient temperature, unless otherwise noted).
Rating
Pin
Symbol
Min
Typ
Max
Unit
Input Power Supply
9
VCC
2.70
5.50V
V
Standby Supply Current Conditions:
INT = CLK_IN = CLK_SPI = CS = H
I/O = MOSI = EN_RPU = H, No Card Inserted
VCC = 3.0 V
VCC = 5.0 V
9
ICCsb
25
35
50
60
mA
DC Operating Current
CLK_IN = Low, All Card Pins Unloaded
@ VCC = 3.3 V, CRD_VCC = 5.0 V
@ VCC = 5.5 V, CRD_VCC = 5.0 V
9
ICCop
0.5
1.5
mA
VCC Under Voltage DetectionHigh
VCC Under Voltage DetectionLow
9
VCCLH
VCCLL
VCCPOR
2.20
2.00
1.50
2.70
2.60
2.20
V
Output Card Supply Voltage
@ 2.7 V < VCC < 5.5 V
CRD_VCC = 1.8 V @ Iload = 35 mA
CRD_VCC = 3.0 V @ Iload = 60 mA
CRD_VCC = 5.0 V @ Iload = 65 mA
13
VC2H
VC3H
VC5H
1.65
2.75
4.75
1.80
3.00
5.00
1.95
3.25
5.25
V
Maximum Continuous Output Current
@ CRD_VCC = 1.8 V
@ CRD_VCC = 3.0 V
@ CRD_VCC = 5.0 V
13
ICC
35
60
65
mA
Output Over Current Limit
VCC = 3.3 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V
VCC = 5.0 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V
13
Iccov
100
150
mA
Output Dynamic Peak Current
@ CRD_VCC = 1.8 V, 3.0 V or 5.0 V, Cout = 10 mF
13
Iccd
100
mA
Output Card Supply Voltage Ripple
@ VCC = 3.6 V, Lout = 22 mH, Cout1 = Cout2 = 4.7 mF
Ceramic X7R, Iout = 55 mA
CRD_VCC = 5.0 V
CRD_VCC = 3.0 V (Note 4)
CRD_VCC = 1.8 V
13
35
mV
Output Card Supply Turn On Time @
Lout = 22 mF, Cout1 = 10 mF Ceramic
VCC = 2.7 V, CRD_VCC = 5.0 V
13
VCCTON
500
ms
Output Card Supply Shut Off Time @
Cout1 = 10 mF, Ceramic
VCC = 2.7 V, CRD_VCC = 5.0 V, VCCOFF < 0.4 V
13
VCCTOFF
100
250
ms
4. Ceramic X7R, SMD type capacitors are mandatory to achieve the CRD_VCC specifications. When an electrolytic capacitor is used, the
external filter must include a 220 nF, max 50 mW ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum.
Depending upon the PCB layout, it might be necessary to use two 4.7 mF/6.0 V/ceramic/X5R/SMD 0805 in parallel, yielding an improved
CRD_VCC ripple over the temperature range.
5. Pulsed current, according to ISO78163, paragraph 4.3.2.
6. No function externally available during the VCC POR sequence.
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