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| 型号： | NCP1910A65DWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/37页 |
| 文件大小： | 0K |
| 描述： | IC COMBO CTLR ATX 24-SOIC |
| 标准包装： | 1 |
| 模式： | 连续导电（CCM） |
| 频率 - 开关： | 245 kHz |
| 电流 - 启动： | 100µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽）23 引线 |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 标准包装 |
| 其它名称： | NCP1910A65DWR2GOSDKR |
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NCP1910
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to +125 ° C, Max T J = 150 ° C,
V CC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
POWER FACTOR CORRECTION
LINE BROWN ? OUT DETECTION
V LBO(PD)
t LBO(Pdlimit)
t PFCflag
t LBO(Pdblank)
Pull Down V LBO Threshold
Pull Down V LBO Time Limitation
Time Delay to Confirm that V CTRL is the maximum to Pull down V LBO
Pull Down V LBO Blanking Time
12
?
?
?
1.8
4.5
2.5
55
2
5
5
77
2.2
6.1
7.5
90
V
ms
ms
ms
CURRENT MODULATION
I M1
I M2
Multiplier Output Current (V CTRL =V CTRL(max) – 0.2 V , V LBO = 3.6 V,
I CS = 50 m A)
Multiplier Output Current (V CTRL =V CTRL(max) – 0.2 V , V LBO = 1.2 V,
I CS = 150 m A)
11
11
46
15
58
19
72
24.5
m A
OVER ? VOLTAGE PROTECTION
V OVP1
V OVP1H
t OVP1
V OVP2
K OVPH
t DELOVP2
I b,OVP2
Internal Auto Recovery Over Voltage Threshold
Hysteresis of Internal Auto Recovery Over Voltage Threshold
(Note 4)
Propagation Delay (V FB = 108% V PREF ) to Drive Low
External Latched Over Voltage Threshold
The difference between V OVP2 and V OVP1 over V PREF ((V OVP2 ?
V OVP1 )/V PREF )
External Latched OVP Integrating Filter Time Constant
Input bias current, OVP2
9
9
9, 18
8
?
?
8
2.536
?
?
2.595
?
?
?
2.615
44
500
2.675
2
20
10
2.694
60
?
2.755
?
?
?
V
mV
ns
V
%
m s
nA
UNDER ? VOLTAGE PROTECTION
V UVP(on) /V PREF UVP Activate Threshold Ratio
V UVP(off) /V PREF UVP Deactivate Threshold Ratio
9
9
4
6
8
12
12
18
%
%
V UVP(H)
t UVP
UVP Lockout Hysteresis
Propagation Delay (V FB < 8 % V PREF ) to Drive Low
9
9 ? 18
?
?
4
7
?
?
%
m s
PFC ABNORMAL
t PFCabnormal
PFC Abnormal Delay Time (V CTRL = V CTRL(max) or V CTRL =
V CTRL(min) – 0.1 V)
?
1
1.5
2.1
sec
LLC CONTROL SECTION
OSCILLATOR
F Lsw,min
F Lsw
F Lsw,max
DC L
V refRt
R SS
SS RST
V Skip
V skip,hyste
Minimum switching frequency, Rt = 70 k W on R t pin
switching frequency, DT L = 300 ns, Rt = 7 k W on R t pin
Maximum switching frequency, DT L = 300 ns, Rt = 3.5 k W on R t pin
Operating Duty ? Cycle symmetry
Reference voltage for oscillator charging current generation
Discharge switch resistance
Soft ? start reset voltage
Skip cycle threshold, B version only
Hysteresis level on skip cycle comparator, B version only
2
2
2
23, 20
2
1
1
16
16
24.25
208
424
48
3.33
?
?
350
?
25
245
500
50
3.5
70
200
400
50
25.75
282
575
52
3.67
?
?
450
?
kHz
kHz
kHz
%
V
W
mV
mV
mV
3. In normal operation, when the power supply is un ? plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,
when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge
slope. However, if for an unknown reason the PFC is disabled (fault, short ? circuit), the PG pin immediately opens and if sufficient voltage
is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.
4. Guaranteed by design.
http://onsemi.com
10
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